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riscv-tests

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riscv-tests is an open-source, Assembly-language collection of RISC-V compliance/ISA test programs maintained in the riscv-software-src/riscv-tests GitHub repository (≈1.2k stars, ≈551 forks as of 2025). It is widely adopted as a standard directed-test benchmark within RISC-V core verification flows, where it is executed alongside riscv-arch-tests under CI pipelines to verify Instruction Set Architecture (ISA) compliance and core functionality.

First seen 6/25/2026
Last seen 6/25/2026
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riscv-tests

Overview

riscv-tests is a public test-suite repository under the riscv-software-src GitHub organization. It is primarily written in Assembly and serves as a community-maintained collection of directed tests used to validate RISC-V processor implementations against the Instruction Set Architecture (ISA) specification.

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Directed Testing implements → 70% 1e
As part of the multi-level strategy, the initial phase of directed testing executes the riscv-tests compliance suite.

CITATIONS

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[1] riscv-tests is a public Assembly-language test repository (riscv-software-src/riscv-tests) with ~1,207 stars and ~551 forks, last updated 2026-06-25. riscv-software-src/riscv-tests (GitHub)
[2] riscv-tests serves as a standard compliance test suite, executed in automated Jenkins CI pipelines alongside riscv-arch-tests to verify ISA conformance of a DUT. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)
[3] riscv-tests is part of a multi-layered verification flow that begins with directed compliance testing, followed by CoreMark/Dhrystone/OS-boot benchmarks, and finally constrained-random RISCV-DV tests with UVM functional coverage. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)
[4] Combined with riscv-arch-tests and RISCV-DV, the verification coverage targets ISA opcodes, extensions (F, D, C), and CSR interactions. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)