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riscv-tests

CodeArtifact WIKI v1 · 6/25/2026

riscv-tests is an open-source, Assembly-language collection of RISC-V compliance/ISA test programs maintained in the riscv-software-src/riscv-tests GitHub repository (≈1.2k stars, ≈551 forks as of 2025). It is widely adopted as a standard directed-test benchmark within RISC-V core verification flows, where it is executed alongside riscv-arch-tests under CI pipelines to verify Instruction Set Architecture (ISA) compliance and core functionality.

riscv-tests

Overview

riscv-tests is a public test-suite repository under the riscv-software-src GitHub organization. It is primarily written in Assembly and serves as a community-maintained collection of directed tests used to validate RISC-V processor implementations against the Instruction Set Architecture (ISA) specification.

Repository statistics (as recorded in the public GitHub metadata):

  • Language: Assembly
  • Stars: ~1,207
  • Forks: ~551
  • Last updated: 2026-06-25

Role in Verification Methodology

riscv-tests functions as a standard compliance test suite in RISC-V processor verification. It is typically executed alongside riscv-arch-tests (the official architectural test suite) inside an automated Jenkins Continuous Integration (CI) pipeline. Together they serve as established benchmarks for verifying that the ISA is correctly implemented by a given core under test (DUT).

In a representative multi-layered RISC-V verification flow (e.g., the NaxRiscv SoC lockstep methodology), riscv-tests is the entry point of the verification process:

  1. Compliance / directed testing phase — riscv-tests and riscv-arch-tests are run as the first stage to confirm basic ISA conformance.
  2. Real-world benchmarking phase — benchmarks such as CoreMark and Dhrystone, plus OS boot sequences (FreeRTOS, Linux boot), are executed to assess software/hardware integration.
  3. Constrained-random testing phase — tools such as RISCV-DV generate randomized assembly programs targeting edge cases (misaligned instructions, RD/RS dependencies, pipeline hazards, memory-access violations, unhandled interrupts), with UVM-based functional-coverage analysis closing the loop.

Characteristics as a Test Suite

  • Form: Assembly-language directed test programs.
  • Purpose: Verify correctness of instruction execution and CSR (Control and Status Register) behavior against the ISA spec.
  • Scope of coverage: When combined with arch-tests and RISCV-DV, the suite covers opcodes, ISA extensions (such as F, D, C), and interactions with system registers (CSRs).
  • Integration model: Designed to be invoked from automated CI frameworks; results feed into regression dashboards and coverage reports.

Relationship to Other Techniques

  • Directed testing — riscv-tests is itself a canonical example of the directed-testing technique: each test targets a specific instruction, opcode, or corner case, with an expected outcome hard-coded or hand-verified.
  • Compliance verification — It pairs with riscv-arch-tests, which is the architectural test suite published by the RISC-V International organization.
  • Random test generation — It complements (rather than replaces) random test generators like RISCV-DV, which probe more complex interactions that directed tests cannot easily enumerate.

See Also

Repository

LINKED ENTITIES

1 links
Directed Testing IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] riscv-tests is a public Assembly-language test repository (riscv-software-src/riscv-tests) with ~1,207 stars and ~551 forks, last updated 2026-06-25. riscv-software-src/riscv-tests (GitHub)
[2] riscv-tests serves as a standard compliance test suite, executed in automated Jenkins CI pipelines alongside riscv-arch-tests to verify ISA conformance of a DUT. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)
[3] riscv-tests is part of a multi-layered verification flow that begins with directed compliance testing, followed by CoreMark/Dhrystone/OS-boot benchmarks, and finally constrained-random RISCV-DV tests with UVM functional coverage. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)
[4] Combined with riscv-arch-tests and RISCV-DV, the verification coverage targets ISA opcodes, extensions (F, D, C), and CSR interactions. Comprehensive lockstep verification for NaxRiscv SoC integrating ... (HAL)