Synopsys VCS

Synopsys VCS is an RTL simulation tool used in hardware verification workflows. In the MorFuzz processor-fuzzing evaluation, the authors describe using Synopsys VCS as an "industry-standard commercial tool" to simulate hardware RTL designs. Their flow translates hardware modules to Verilog and compiles them into a host executable binary through the Synopsys VCS RTL simulator.

Use in RISC-V verification flows

The RISCV-DV project is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. Its documentation states that running the generator requires an RTL simulator supporting SystemVerilog and UVM 1.2, and lists Synopsys VCS among the simulators with which the generator has been verified, alongside Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO.

Constraint solving and profiling

Evidence from an AMD microcode stimulus-generation article describes use of the VCS constraint solver in a constrained-random instruction generator context. The article discusses splitting a large opcode randomization problem into multiple smaller opcode-category classes to reduce randomization problem size, with shared data members and constraints placed in a base instruction class and category-specific constraints placed in child classes.

The same article describes the VCS constraint profiler as a tool for analyzing generator performance in terms of runtime and memory. Runtime details are reported in three views: cumulative randomize calls, per-randomize-call data, and per-partition data. The article also notes that VCS can partition a randomize call into several partitions when unrelated random variables occur within the same randomize call, allowing unrelated variables to be solved independently.

Scope of documented evidence

The provided evidence supports VCS as an RTL simulator used for Verilog-based hardware simulation, as a verified simulator option for RISCV-DV, and as the context for a constraint solver/profiler used in constrained-random stimulus generation. No provided evidence supports additional claims about product packaging, supported language versions beyond the RISCV-DV simulator requirement context, licensing, performance benchmarks, or specific command-line usage.