Hierarchical Constrained-Random Test Generation

Technique

Hierarchical constrained-random test generation structures a constrained-random stimulus generator so that a high-level choice, such as an opcode category, is made before solving a smaller category-specific constraint problem. In the AMD x86 microcode-stimulus example, splitting a single opcode class into a base class plus category child classes improved runtime and memory while preserving distribution control and test-level knob control.

First seen 5/24/2026

Last seen 6/4/2026

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WIKI

Overview

Hierarchical constrained-random test generation is a verification-stimulus technique in which a generator first chooses a high-level category and then randomizes a smaller, category-specific object. In the AMD x86 opcode-generation example, instructions were randomized by first choosing the opcode category so the constraint solver only had to consider constraints specific to that category. This simplified the problem and improved memory and speed without sacrificing distribution or test-level control. [C1]

Generator architecture

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RELATIONSHIPS

29 connections

Sequential Randomization compares with → 95% 4e

The article contrasts hierarchical constrained-random test generation with traditional sequential randomization methods.

SystemVerilog Random Sequence Construct uses → 95% 3e

The upper layer of the generator uses a SystemVerilog random sequence construct with weighted knobs.

SystemVerilog Constraint Language uses → 95% 3e

The hierarchical constrained-random approach leverages the SystemVerilog constraint language to describe microcode instructions.

CPU Verification uses → 2e

Hierarchical constrained-random test generation is applied in the context of CPU verification.

weighted knobs for test control uses → 95% 2e

The generator uses weighted knobs to control the distribution of high-level items and opcode categories.

op_gen.sv ← implements 90% 2e

op_gen.sv is the source file implementing the opcode generator with hierarchical constrained-random approach.

Corner Case Coverage uses → 90% 2e

Hierarchical constrained-random test generation is designed to achieve corner case coverage through biasing.

Synopsys VCS uses → 95% 2e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver for generation.

Test Knobs uses → 90% 2e

The instruction generator is controlled by a set of knobs to direct stimulus generation.

Weighted Knobs uses → 95% 2e

Hierarchical constrained-random test generation uses weighted knobs to control instruction distribution.

Instruction Field Distribution uses → 1e

Hierarchical constrained-random test generation provides control over instruction field distribution.

op_gen.sv ← uses 1e

op_gen.sv uses hierarchical constrained-random test generation to implement the opcode generator.

Testbench uses → 1e

Hierarchical constrained-random test generation is integrated into a testbench environment for performance measurement.

AMD ← uses 1e

AMD uses hierarchical constrained-random test generation in its CPU verification flow.

microcode test sequence generation implements → 95% 1e

The hierarchical constrained-random approach is used to generate microcode test sequences.

Synopsys VCS Constraint Solver uses → 98% 1e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver for optimal distribution and biasing.

object-oriented verification methodology implements → 92% 1e

The hierarchical constrained-random test generation uses an object-oriented approach with base and sub-classes.

opcode category partitioning implements → 92% 1e

By partitioning constraints hierarchically into smaller groups of opcodes, memory requirements were reduced.

instruction field randomization implements → 90% 1e

The hierarchical approach randomizes instruction fields with precise control over distribution.

wrapper class architecture uses → 82% 1e

Wrapper class architecture is optionally used when test layer directly controls items in sub-classes.

Object-Oriented Constraint Partitioning implements → 90% 1e

The hierarchical approach implements object-oriented constraint partitioning to reduce memory and improve performance.

Opcode Generator introduces → 90% 1e

The hierarchical approach introduces the opcode generator as its core artifact.

Multi-Class Randomization compares with → 90% 1e

Multi-class randomization is compared with single-class in terms of runtime and memory performance.

Weighted Distribution uses → 90% 1e

The generator uses weighted distributions to control opcode type distribution.

Directed Test Generation ← compares with 85% 1e

The hierarchical constrained-random approach replaces hand-written directed tests in microprocessor verification.

Constraint Solver uses → 1e

Hierarchical constrained-random test generation uses a constraint solver to generate solutions.

SystemVerilog random sequence uses → 1e

Hierarchical constrained-random test generation uses a SystemVerilog random sequence construct in its upper layer.

Object-Oriented Verification implements → 1e

Hierarchical constrained-random test generation implements object-oriented verification principles through class hierarchies.

Opcode Generation uses → 1e

Hierarchical constrained-random test generation is applied to opcode generation.

LINKED ENTITIES

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Synopsys VCS USES Extracted graph relationship

SystemVerilog Constraint Language USES Extracted graph relationship

SystemVerilog Random Sequence Construct USES Extracted graph relationship

Test Knobs USES Extracted graph relationship

Weighted Distribution USES Extracted graph relationship

Sequential Randomization COMPARES_WITH Extracted graph relationship

Directed Test Generation COMPARES_WITH Extracted graph relationship

op_gen.sv IMPLEMENTS Extracted graph relationship

Corner Case Coverage USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] C1: Randomizing instructions by first choosing the opcode category simplified the constraint problem and improved memory and speed without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver

[2] C2: The multi-class architecture split the opcode class into smaller classes, divided opcodes into categories mapped to knobs or weights, used a base class for common members/methods/constraints, and used child classes for opcode-specific constraints. Generating AMD microcode stimuli using VCS constraint solver

[3] C3: The generator was controlled by knobs or switches; the upper-layer random sequence chose the opcode category first, and a wrapper-class two-phase scheme was suggested when tests directly control lower-level items. Generating AMD microcode stimuli using VCS constraint solver

[4] C4: Serial randomization met speed and memory goals but lacked overall distribution control, causing skewed results and more seeds/simulations; simple constrained randomization solved distribution but hit speed and memory limits on the x86 instruction set. Generating AMD microcode stimuli using VCS constraint solver

[5] C5: The VCS constraint profiler reported cumulative, individual, and partition runtime data; `op_gen.sv` line 4308 ran 7,104 times and consumed 44 seconds, while another 3.2-second call occurred only twice; VCS can partition unrelated random variables for independent solving. Generating AMD microcode stimuli using VCS constraint solver

[6] C6: The multiple-class architecture improved runtime and memory; RACE showed a 4x speedup, BDD showed a 2x speedup, BDD memory was a focus because it elaborates the full solution space, and the new implementation had 7x fewer constraints. Generating AMD microcode stimuli using VCS constraint solver