Synopsys VCS Constraint Solver

Tool

Synopsys VCS Constraint Solver is described in the provided evidence as a SystemVerilog constrained-random solving technology used to generate AMD x86 microcode stimuli with controllable distributions, profiling support, and alternative solver behavior such as default RACE and BDD modes.

First seen 5/25/2026

Last seen 6/4/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

The Synopsys VCS Constraint Solver was used in an AMD/Synopsys case study to generate microcode test sequences for x86 instruction verification. The approach used SystemVerilog constraint-language constructs to describe legal combinations of opcode attributes and to control value distributions for individual fields. The motivation was to replace sequential field randomization, which the authors reported produced verbose code, redundant code, and limited distribution control. [C1]

Generator architecture

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

5 connections

Hierarchical Constrained-Random Test Generation ← uses 98% 1e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver for optimal distribution and biasing.

RACE Solver ← part of 85% 1e

The RACE solver is one of the solvers available within VCS.

VCS 2009.12 ← part of 85% 1e

VCS 2009.12 is a specific release version of the Synopsys VCS tool.

BDD Solver ← part of 85% 1e

The BDD solver is one of the solvers available within VCS.

VCS Constraint Profiler ← part of 85% 1e

The VCS constraint profiler is a component of the VCS toolset.

CITATIONS

9 sources

9 citations — click to expand

[1] C1: The Synopsys VCS Constraint Solver was used for constrained-random AMD x86 microcode stimulus generation with SystemVerilog constraints and distribution control, addressing limitations of sequential randomization. Generating AMD microcode stimuli using VCS constraint solver

[2] C2: The generator architecture used an upper SystemVerilog random sequence layer with weighted knobs and a lower opcode-class randomization layer, with tests supplying weighted values for instruction mix control. Generating AMD microcode stimuli using VCS constraint solver

[3] C3: The single-class opcode model was flexible but could be slow because it presented the solver with many random variables and constraints; the reported class had about 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver

[4] C4: The multi-class architecture used a base class for global constraints and subclasses for related opcode groups, reducing memory requirements and improving performance by partitioning constraints hierarchically. Generating AMD microcode stimuli using VCS constraint solver

[5] C5: In BDD mode, the solver elaborates the entire solution space before selecting a solution, can consume significant memory and time, caches the solution space, and is useful when repeated randomize calls occur and memory is not excessive. Generating AMD microcode stimuli using VCS constraint solver

[6] C6: VCS provided constraint profile data for runtime and memory, and VCS 2009.12 included testcase extraction to automatically extract the slowest partition from each randomize call. Generating AMD microcode stimuli using VCS constraint solver

[7] C7: The multi-class architecture was faster than the single-class architecture for both solvers and tested opcodes, with a 4x speedup for default RACE and 2x for BDD; BDD memory use was significantly improved and RACE memory was typically smaller. Generating AMD microcode stimuli using VCS constraint solver

[8] C8: The reported acceleration and memory reduction were mainly due to a smaller set of variables and constraints; the new implementation had 7x fewer constraints than the original. Generating AMD microcode stimuli using VCS constraint solver

[9] C9: The article concludes that choosing an opcode category before randomizing simplified the constraint problem and improved memory and speed without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver