RACE Solver

Tool

RACE Solver is identified in the provided evidence as the default constraint solver used in a VCS-based constrained-random stimulus generation comparison for AMD x86 opcode generation. In that study, a multiple-class opcode-generation architecture improved runtime with RACE by 4x, while RACE memory use was described as typically smaller and not a limiting factor compared with BDD-solver memory behavior.

First seen 5/26/2026

Last seen 6/4/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

RACE Solver is described in the evidence as the default solver in a VCS constraint-solving workflow used for constrained-random generation of AMD x86 microcode/opcode stimuli. The reported work compared solver behavior across opcode-generation architectures and contrasted RACE with a BDD solver in terms of runtime and memory characteristics. [C1]

Use in constrained-random opcode generation

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RELATIONSHIPS

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Synopsys VCS part of → 90% 1e

The RACE solver is a constraint solver available within Synopsys VCS.

Multi-Class Randomization ← uses 90% 1e

Multi-class architecture performance was measured using the RACE solver.

Single-Class Randomization ← uses 90% 1e

Single-class architecture performance was measured using the RACE solver.

Synopsys VCS Constraint Solver part of → 85% 1e

The RACE solver is one of the solvers available within VCS.

CITATIONS

8 sources

8 citations — click to expand

[1] RACE is identified as the default solver in the VCS comparison, and the study compares it with a BDD solver. Generating AMD microcode stimuli using VCS constraint solver

[2] Serial randomization had acceptable speed and memory but caused skewed distribution, while simple constrained randomization addressed distribution but encountered speed and memory limits on the complex x86 instruction set. Generating AMD microcode stimuli using VCS constraint solver

[3] Choosing the opcode category before randomizing instructions reduced the solver problem to category-specific constraints and improved speed and memory without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver

[4] The multiple-class architecture was faster with both solvers; the default RACE solver showed a 4x speedup, and the BDD solver showed a 2x speedup. Generating AMD microcode stimuli using VCS constraint solver

[5] Memory requirements improved with the multiple-class architecture, and RACE memory consumption was typically smaller and not a limiting factor, so memory was measured only for the BDD solver. Generating AMD microcode stimuli using VCS constraint solver

[6] The newer multiple-class implementation had 7x fewer constraints than the original, which was identified as the main reason for acceleration and reduced memory use. Generating AMD microcode stimuli using VCS constraint solver

[7] The evaluation used profile data and a small repeated-randomization testbench to isolate solver CPU time, and VCS 2009.12 provided automatic extraction of the slowest partition from each randomize call. Generating AMD microcode stimuli using VCS constraint solver

[8] The BDD solver elaborates the entire solution space before selecting a solution, which can consume significant memory and time, though caching can speed subsequent calls; it works well when memory is manageable and calls repeat often. Generating AMD microcode stimuli using VCS constraint solver