Multi-Class Randomization
TechniqueMulti-Class Randomization is a constrained-random instruction-generation technique that reduces solver complexity by splitting a large opcode class into multiple category-specific child classes. In the cited AMD microcode-stimulus case study, choosing the opcode category first reduced the active variables and constraints, producing faster runtime and lower memory use than a single-class architecture.
First seen 5/26/2026
Last seen 6/5/2026
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Overview
Multi-Class Randomization reduces the size of a constrained-random generation problem by splitting one large opcode class into multiple smaller classes. In the cited instruction-generator architecture, opcodes were divided into categories that matched the knobs or weights exposed by the test interface. [C1]
The technique uses a base instruction class for data members and methods common to all instruction types, while each opcode-category child class contains only the constraints specific to that category. [C2]
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16 connectionsThe VCS Constraint Profiler was used to evaluate and compare the performance of multi-class randomization.
Multi-class randomization is directly compared to single-class randomization in terms of runtime and memory performance.
Multi-class randomization extends single-class randomization by splitting the opcode class into multiple smaller classes for better performance.
Multi-Class Randomization uses a base instruction class containing common data members and methods.
A wrapper class may be required when the test layer directly controls items in the lower levels of the multi-class architecture.
Multi-class randomization uses object-oriented verification by organizing opcodes into a class hierarchy.
Wrapper-class randomization is an architectural variant that adds a wrapper class to handle test-layer constraints over sub-classes.
The multi-class generator is controlled by knobs or switches allowing test writers to generate constrained stimulus.
Multi-class randomization was developed by splitting the single class into multiple smaller classes to reduce the randomization problem size.
Multi-class randomization is an implementation of constrained-random verification for CPU opcode generation.
Multi-class randomization is compared with single-class in terms of runtime and memory performance.
Each opcode category child class uses implication operators based on the opcode type.
Multi-class randomization splits opcodes into categories corresponding to child classes.
Multi-class architecture performance was measured using the RACE solver.
Multi-class architecture performance was measured using the BDD solver.
Multi-class randomization splits opcodes into a hierarchy of classes.
CITATIONS
12 sources12 citations — click to expand
[1] Multi-Class Randomization reduces a constrained-random opcode-generation problem by splitting the opcode class into smaller category classes mapped to test-interface knobs or weights. Generating AMD microcode stimuli using VCS constraint solver
[2] The architecture uses a base instruction class for common data, common constraints, and common methods, with child classes holding category-specific constraints. Generating AMD microcode stimuli using VCS constraint solver
[3] Serial x86 opcode generation had acceptable speed and memory but caused skewed distributions, while a simple constrained-random approach solved distribution but reached speed and memory limits. Generating AMD microcode stimuli using VCS constraint solver
[4] Each opcode-category child class used constraints specific to that opcode set and retained a structure similar to the original single-class code, including implication operators based on opcode type. Generating AMD microcode stimuli using VCS constraint solver
[5] The upper-layer random sequence was controlled by knobs, chose the opcode category first, and then allocated the correct object type. Generating AMD microcode stimuli using VCS constraint solver
[6] If the test layer directly controls subclass items, a wrapper class may be required to randomize test-controlled variables before allocating and randomizing the correct subclass. Generating AMD microcode stimuli using VCS constraint solver
[7] The multi-class implementation had seven times fewer constraints than the original, enabling more efficient solving. Generating AMD microcode stimuli using VCS constraint solver
[8] Runtime for the multi-class architecture was faster with both solvers, with a 4x speedup for the default RACE solver and a 2x speedup for the BDD solver. Generating AMD microcode stimuli using VCS constraint solver
[9] Memory requirements were significantly better for the multi-class architecture; the study measured BDD memory because RACE memory was typically smaller and not limiting. Generating AMD microcode stimuli using VCS constraint solver
[10] The VCS constraint profiler provided runtime information for cumulative randomize calls, individual randomize calls, and partitions. Generating AMD microcode stimuli using VCS constraint solver
[11] The BDD solver elaborates the entire solution space before choosing a solution, which can consume substantial memory and time, with caching used to speed later randomizations. Generating AMD microcode stimuli using VCS constraint solver
[12] Choosing the opcode category first simplifies the randomization problem because only constraints specific to that category are present, improving memory and speed without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver