Single-Class Randomization

Technique

Single-Class Randomization is a constrained-random verification technique in which one instruction or opcode class contains the random variables and constraints for all supported opcodes. It provides high modeling flexibility and direct constraint interactions across fields, but can become slow and memory-intensive when the instruction space is large because the constraint solver must handle many variables and a large constraint set in one randomization problem.

First seen 5/26/2026

Last seen 6/5/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Single-Class Randomization is a constrained-random instruction-generation style in which a single class contains all opcodes and their associated constraints. In the AMD/Synopsys microcode stimulus generator described in the evidence, the initial prototype used one class with constraints for all opcodes, relying on SystemVerilog constraint constructs to describe legal instruction attribute combinations and control value distributions. [C1]

Architecture

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RELATIONSHIPS

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VCS Constraint Profiler ← evaluates 90% 7e

The VCS Constraint Profiler was used to evaluate and compare the performance of single-class randomization.

Multi-Class Randomization ← compares with 98% 5e

Multi-class randomization is directly compared to single-class randomization in terms of runtime and memory performance.

Multi-Class Randomization ← extends 95% 4e

Multi-class randomization extends single-class randomization by splitting the opcode class into multiple smaller classes for better performance.

Multi-Class Randomization ← derived from 95% 1e

Multi-class randomization was developed by splitting the single class into multiple smaller classes to reduce the randomization problem size.

RACE Solver uses → 90% 1e

Single-class architecture performance was measured using the RACE solver.

BDD Solver uses → 90% 1e

Single-class architecture performance was measured using the BDD solver.

CITATIONS

8 sources

8 citations — click to expand

[1] C1: The initial constrained-random microcode generator used a single class containing constraints for all opcodes, and SystemVerilog constraint constructs were used to describe instruction attribute combinations and value distributions; this addressed flaws of sequential randomization. Generating AMD microcode stimuli using VCS constraint solver

[2] C2: The generator architecture used an upper layer with weighted knobs and a lower opcode class randomized with additional constraints and weights to control opcode-type distribution. Generating AMD microcode stimuli using VCS constraint solver

[3] C3: The single-class implementation used random variables and implication constraints to generate legal opcodes, with opcode type as a key data member controlling instruction type. Generating AMD microcode stimuli using VCS constraint solver

[4] C4: Single-class randomization is flexible because constraints can be applied between any opcode-class data members, but may be slow because the solver sees many random variables and complex constraints; the documented class had about 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver

[5] C5: A simple constrained-random approach solved distribution issues but reached speed and memory limits for the complex x86 instruction set, reducing simulation performance. Generating AMD microcode stimuli using VCS constraint solver

[6] C6: In the reported comparison, the multiple-class architecture was faster than the single-class architecture with both solvers; RACE showed a 4x speedup and BDD showed a 2x speedup, and BDD memory requirements were significantly better for the multiple-class architecture. Generating AMD microcode stimuli using VCS constraint solver

[7] C7: The performance and memory improvement of the newer implementation was attributed to a smaller set of variables and constraints; it had 7x fewer constraints than the original implementation. Generating AMD microcode stimuli using VCS constraint solver

[8] C8: The multiple-class alternative split opcodes into categories, used a base class for common data and constraints, placed category-specific constraints in child classes, and simplified the solver problem by first choosing the opcode category. Generating AMD microcode stimuli using VCS constraint solver