CPU verification
ConceptCPU verification is the functional verification of CPU cores, addressing the corner cases created by complex performance features such as pipelines, multiple instruction issue, out-of-order execution, branch prediction, and caching. The evidence covers constrained-random instruction-stream execution, multi-core shared-resource stimulus generation, constraint-solver performance tradeoffs in opcode generation, and LLM-aided FPGA-accelerated frameworks such as ISAAC that combine multi-agent stimulus generation with parallel co-simulation to detect previously unknown bugs in mature CPUs.
First seen 5/27/2026
Last seen 7/19/2026
Evidence 11 chunks
Wiki v5
WIKI
Overview
CPU verification is the functional verification of CPU cores, motivated by the fact that performance-enhancing microarchitectural features can threaten functional correctness. The evidence identifies examples such as Pipeline, Multiple Instruction Issue, Out-of-Order Execution, Branch Prediction, and memory-access acceleration through Cache. These features create corner cases that require specialist verification techniques. [C1]
Constrained-random instruction-stream execution
NEIGHBORHOOD
2 nodes · 1 edgesgraph · CPU Verification · depth=1
RELATIONSHIPS
10 connectionsSail ISA specifications are used in CPU verification workflows.
Hierarchical constrained-random test generation is applied in the context of CPU verification.
ISAAC targets and supports CPU verification workflows.
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism ← evaluates 95% 2e
The paper targets and evaluates CPU verification as its main application domain.
CPU verification uses ISA specifications as the reference for correctness.
CPU Verification uses formal verification as one of its techniques.
CPU verification uses coverage-driven verification approaches.
CPU verification methodologies often employ UVM
ISAAC implements CPU verification using LLM-aided FPGA parallelism.
The paper applies end-to-end CPU verification using ISA-Formal.
LINKED ENTITIES
9 linksUVM USES Extracted graph relationship
asureISG MENTIONS asureISG is identified in the TVS evidence as an instruction-stream generation tool for CPU verification.
pipeline MENTIONS Pipelines are cited as a CPU performance feature that can break functional correctness.
Multiple Instruction Issue MENTIONS Multiple instruction issue is cited as a CPU performance feature requiring specialist verification.
out-of-order execution MENTIONS Out-of-order execution is cited as a CPU performance feature requiring specialist verification.
Branch Prediction MENTIONS Branch prediction is cited as a CPU performance feature requiring specialist verification.
cache MENTIONS Caches are cited as a memory-access acceleration feature and as a shared resource in multi-core CPUs.
ISAAC MENTIONS ISAAC is presented in the arxiv evidence as an LLM-aided, FPGA-accelerated CPU verification framework that demonstrated up to 17,536x speedup and detected previously unknown bugs.
Instruction Set Simulator MENTIONS ISS is used in ISAAC's decoupled co-simulation architecture with the DUT.
CITATIONS
12 sources12 citations — click to expand
[1] CPU cores implement complex performance enhancements such as pipelines, multiple instruction issue, out-of-order execution, branch prediction, and caching that can break functional correctness and require specialist verification techniques including constrained-random instruction-stream execution. TVS extends CPU Verification Capability - Design And Reuse
[2] TVS developed the asureISG instruction-stream generation tool and a CPU verification engineering team to support CPU verification, with asureISG initially supporting single-core CPU verification and planned multi-core enhancement. TVS extends CPU Verification Capability - Design And Reuse
[3] Multi-core CPUs share resources such as caches, motivating tools that generate multiple instruction streams aware of potential bugs in shared-resource management. TVS extends CPU Verification Capability - Design And Reuse
[4] Serial randomization of x86 opcodes achieved desired speed and memory but produced a skewed distribution requiring more seeds and simulations to close coverage. Generating AMD microcode stimuli using VCS constraint solver
[5] A simple constrained-random approach to x86 opcode generation fixed the distribution problem but reached speed and memory limits due to the complexity of the x86 instruction set. Generating AMD microcode stimuli using VCS constraint solver
[6] Randomizing instructions by first choosing the opcode category improved speed and memory use without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver
[7] In VCS BDD solver mode, the entire solution space is elaborated before a solution is selected, consuming substantial memory and time, but the elaborated space is cached to speed later randomization calls; BDD solving works well for CPU opcode generation when memory use is not excessive and the same randomize call occurs many times. Generating AMD microcode stimuli using VCS constraint solver
[8] A multiple-class randomization architecture outperformed a single-class one in runtime (4x speedup with the RACE solver, 2x with the BDD solver) and significantly reduced memory requirements under BDD. Generating AMD microcode stimuli using VCS constraint solver
[9] The multiple-class architecture had 7x fewer constraints than the original, which the source attributes as the main reason for the runtime and memory improvements. Generating AMD microcode stimuli using VCS constraint solver
[10] ISAAC is an LLM-aided, FPGA-accelerated, full-stack CPU verification framework that addresses bottlenecks in front-end stimulus generation (lack of micro-architectural awareness) and back-end simulation (long-running tests, limited visibility) via a multi-agent stimulus engine and a decoupled ISS-DUT co-simulation architecture with a lightweight forward-snapshot mechanism. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[11] ISAAC achieved up to 17,536x speed-up over software RTL simulation on a mature CPU with multiple successful tape-outs and detected several previously unknown bugs, two of which are reported in the paper. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[12] The Alastair Reid Related Work notes page lists CPU verification alongside related ISA-specification tooling such as Sail, LISA, ASL, SLED, and others. ISA specification notes - Alastair Reid Related Work