CPU Verification
ConceptCPU verification is the functional verification of CPU cores, motivated by microarchitectural features such as pipelining, multiple instruction issue, out-of-order execution, branch prediction, and caching that threaten functional correctness. The article covers constrained-random instruction-stream generation (including TVS asureISG and VCS constraint-solver tradeoffs), multi-core shared-resource stimulus generation, differential fuzzing approaches such as DifuzzRTL and ISAAC's LLM-aided, FPGA-accelerated full-stack framework, and differential testing for transient-execution vulnerabilities via SpecDoctor.
First seen 5/27/2026
Last seen 7/30/2026
Evidence 13 chunks
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WIKI
Overview
CPU verification is the functional verification of CPU cores. It is motivated by the fact that performance-enhancing microarchitectural features can threaten functional correctness. Evidence identifies examples such as Pipeline, Multiple Instruction Issue, Out-of-Order Execution, Branch Prediction, and memory-access acceleration through Cache. These features create corner cases that require specialist verification techniques. [C1]
Differential testing as industrial practice
NEIGHBORHOOD
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11 connectionsHierarchical constrained-random test generation is applied in the context of CPU verification.
ISAAC targets and supports CPU verification workflows.
CPU verification uses ISA specifications as the reference for correctness.
Sail ISA specifications are used in CPU verification workflows.
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism ← evaluates 95% 2e
The paper targets and evaluates CPU verification as its main application domain.
CPU Verification uses formal verification as one of its techniques.
DifuzzRTL is applied to CPU verification via differential fuzz testing.
CPU verification uses coverage-driven verification approaches.
ISAAC implements CPU verification using LLM-aided FPGA parallelism.
CPU verification methodologies often employ UVM
The paper applies end-to-end CPU verification using ISA-Formal.
LINKED ENTITIES
11 linkspipeline RELATED_TO TVS source lists pipelining as a performance-enhancing microarchitectural feature that can threaten CPU functional correctness.
DiFuzzRTL EVALUATES Extracted graph relationship
Multiple Instruction Issue RELATED_TO TVS source lists multiple instruction issue as a microarchitectural feature driving CPU verification.
out-of-order execution RELATED_TO TVS source lists out-of-order execution as a microarchitectural feature motivating CPU verification.
Branch Prediction RELATED_TO TVS source lists branch prediction as a microarchitectural feature that can break functional correctness.
cache RELATED_TO TVS source identifies caching as a memory-access acceleration feature driving CPU verification needs, including shared cache management in multi-core contexts.
Test and Verification Solutions Ltd RELATED_TO TVS provides CPU verification capability, services, and tools relevant to the topic.
asureISG RELATED_TO asureISG is TVS's instruction-stream generation tool for CPU verification, initially for single-core with planned multi-core support.
ISAAC RELATED_TO ISAAC is the full-stack LLM-aided CPU verification framework with FPGA parallelism presented in the public context.
SpecDoctor RELATED_TO SpecDoctor is an automated RTL fuzzer for transient-execution vulnerabilities in CPUs, evaluating the same broad goal of CPU verification via differential fuzz testing.
UVM RELATED_TO UVM is referenced as commonly used in verification methodologies that apply to CPU verification environments.
CITATIONS
14 sources14 citations — click to expand
[1] CPU verification is the functional verification of CPU cores, motivated by microarchitectural features such as pipelining, multiple instruction issue, out-of-order execution, branch prediction, and caching that can threaten functional correctness. TVS extends CPU Verification Capability - Design And Reuse
[2] Constrained random instruction stream execution generates small assembler programs for execution on the core to verify corner cases created by complex performance enhancements. TVS extends CPU Verification Capability - Design And Reuse
[3] TVS extended its CPU verification capability with a new Instruction Stream Generation tool called asureISG and a new team of CPU verification engineers. TVS extends CPU Verification Capability - Design And Reuse
[4] asureISG initially supports single CPU core verification but will soon be enhanced with multi-core support; multi-core SoCs share resources such as caches, requiring multiple instruction streams that understand potential bugs in shared-resource management. TVS extends CPU Verification Capability - Design And Reuse
[5] Serial randomization of x86 opcodes achieved desired speed and memory use but suffered a significant distribution problem; results were skewed, requiring many additional seeds and simulations to close coverage. Generating AMD microcode stimuli using VCS constraint solver
[6] A simple constrained-random approach solved the x86 opcode distribution issue but reached speed and memory limits because of the complexity of the x86 instruction set, reducing simulation performance. Generating AMD microcode stimuli using VCS constraint solver
[7] Randomizing x86 instructions by first choosing the opcode category simplified the constraint-solver problem, resulting in improved memory and speed without sacrificing distribution quality or test-level control. Generating AMD microcode stimuli using VCS constraint solver
[8] In BDD solver mode, VCS elaborates the entire solution space of a randomize call before selecting a solution, which can consume substantial memory and time but is cached to speed subsequent calls; BDD works well for CPU opcode generation when memory is not excessive and the same randomize call occurs many times. Generating AMD microcode stimuli using VCS constraint solver
[9] A multiple-class randomization architecture was faster than a single-class architecture with either VCS solver: a 4x speedup with the default RACE solver and a 2x speedup with the BDD solver, with significantly better BDD memory requirements. Generating AMD microcode stimuli using VCS constraint solver
[10] The multiple-class implementation presented 7x fewer constraints to the VCS solver than the original, allowing the solver to calculate solutions more efficiently and yielding the acceleration and memory reduction. Generating AMD microcode stimuli using VCS constraint solver
[11] CPU verification is a critical, time-intensive, and labor-consuming bottleneck in IC development; industrial practice relies on differential testing, and the front-end stimulus generation and back-end simulation stages each have pipeline bottlenecks; ISAAC is a full-stack LLM-aided framework with FPGA parallelism whose multi-agent stimulus engine uses micro-architectural knowledge and historical bug patterns, and whose back-end uses a lightweight forward-snapshot mechanism and decoupled ISS-DUT co-simulation enabling one ISS to drive multiple DUTs in parallel; ISAAC achieved up to 17,536x speed-up over software RTL simulation on a mature, multi-tape-out CPU and detected several previously unknown bugs. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[12] DifuzzRTL is a differential fuzz testing approach for CPU verification that introduces register-coverage as a coverage metric to comprehensively capture RTL state and guide input generation; it instruments register-coverage, randomly generates and mutates ISA-defined instructions, and cross-checks results against an ISA simulator to detect bugs. DiFuzzRTL: Differential Fuzz Testing to Find CPU Bug (S&P 2021)
[13] SpecDoctor is an automated RTL fuzzer for transient execution vulnerabilities in CPUs that uses a single fuzzing template to test Meltdown/Spectre/ForeShadow-style scenarios with multi-phased fuzzing solving individual vulnerability constraints; evaluated on Boom and NutShell-Argo RISC-V CPUs, it found prior-style vulnerabilities plus two new variants Boombard and Birgus, both confirmed by developers. SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities
[14] Alastair Reid's Related Work ISA specification notes page lists CPU verification among topics related to instruction-set architecture specification. ISA specification notes