UVM

Tool

UVM, in the provided evidence, refers to the Universal Verification Methodology used to build modular, scalable, reusable SystemVerilog verification environments. The cited RISC-V vector-accelerator work used a UVM environment with agents, virtual sequences, a scoreboard, Spike co-simulation, RISCV-DV constrained-random binaries, SystemVerilog Assertions, CI regressions, and functional coverage, reporting 3005 errors found and 95.79% functional coverage.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 16 chunks

Wiki v3

WIKI

Overview

UVM is used in the evidence as the Universal Verification Methodology for building a modular, scalable, and reusable verification environment. The cited RISC-V vector-accelerator paper references the Accellera UVM standard and states that UVM was selected because the verification tools had to be shareable with partners and reusable for next-generation designs. [UVM role]

In that case study, the design under test was a RISC-V based decoupled Vector Processing Unit (VPU) connected to a scalar processor core through the Open Vector Interface (OVI). The verification infrastructure consisted of a UVM environment, step-by-step co-simulation of vector instructions using Spike as a reference model, automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. [VPU verification infrastructure]

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NEIGHBORHOOD

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RELATIONSHIPS

19 connections

Co-simulation implements → 95% 2e

The UVM environment performs step-by-step co-simulation of all vector instructions with Spike.

UVM scoreboard implements → 95% 2e

The UVM environment includes a scoreboard that compares VPU results with reference model results.

Functional Coverage implements → 95% 2e

The UVM environment implements a functional coverage plan to measure verification completeness.

SystemVerilog Assertions uses → 93% 2e

SystemVerilog Assertions are used alongside the UVM testbench to improve observability and detect bugs.

spike uses → 97% 2e

The UVM environment uses Spike as its reference model for co-simulation.

riscv-dv uses → 93% 2e

RISCV-DV is used within the UVM verification flow to generate random test programs.

Vector Processing Unit (VPU) evaluates → 97% 2e

The UVM environment is used to functionally verify the VPU.

RTL evaluates → 90% 2e

The UVM testbench is used for verifying the RTL design of the vector accelerator.

Functional Verification of a RISC-V Vector Accelerator ← uses 98% 2e

The paper describes a verification approach built on the UVM methodology.

Processor Verification ← uses 92% 2e

UVM test platforms are maintained by major processor vendors for processor verification.

Constrained Random Verification uses → 90% 1e

The UVM-based verification flow uses constrained random verification test sequences.

UVM agent implements → 95% 1e

The UVM environment uses one agent for each OVI sub-interface.

virtual sequence implements → 93% 1e

Virtual sequences are used in the UVM environment to coordinate stimulus across sub-interfaces.

constrained-random instruction generation implements → 93% 1e

UVM is a good framework for constrained-random instruction generation.

simulation-based verification ← uses 90% 1e

UVM is used as the standard for simulation-based verification.

Coverage-Driven Verification implements → 90% 1e

UVM implements coverage-driven verification as a standard methodology for reusable testbench structures.

simulation-based verification implements → 90% 1e

UVM is used as the framework for simulation-based verification.

SystemVerilog uses → 95% 1e

UVM is a class library defined using the syntax and semantics of SystemVerilog.

Functional Coverage uses → 90% 1e

UVM-based verification uses functional coverage as a quality metric.

LINKED ENTITIES

11 links

Co-simulation IMPLEMENTS Extracted graph relationship

UVM scoreboard IMPLEMENTS Extracted graph relationship

UVM agent IMPLEMENTS Extracted graph relationship

virtual sequence IMPLEMENTS Extracted graph relationship

Functional Coverage IMPLEMENTS Extracted graph relationship

SystemVerilog Assertions USES Extracted graph relationship

spike USES Extracted graph relationship

riscv-dv USES Extracted graph relationship

Vector Processing Unit (VPU) EVALUATES Extracted graph relationship

RTL EVALUATES Extracted graph relationship

Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

CITATIONS

17 sources

17 citations — click to expand

[1] UVM role Functional Verification of a RISC-V Vector Accelerator

[2] VPU verification infrastructure Functional Verification of a RISC-V Vector Accelerator

[3] Agent structure Functional Verification of a RISC-V Vector Accelerator

[4] Virtual sequences and synchronization Functional Verification of a RISC-V Vector Accelerator

[5] Agent-maintenance lesson Functional Verification of a RISC-V Vector Accelerator

[6] Scoreboard and Spike Functional Verification of a RISC-V Vector Accelerator

[7] Spike integration Functional Verification of a RISC-V Vector Accelerator

[8] Reduction reference-model exception Functional Verification of a RISC-V Vector Accelerator

[9] RISCV-DV role Functional Verification of a RISC-V Vector Accelerator

[10] RISCV-DV blacklisting Functional Verification of a RISC-V Vector Accelerator

[11] Assertions Functional Verification of a RISC-V Vector Accelerator

[12] Functional coverage plan Functional Verification of a RISC-V Vector Accelerator

[13] Coverage results Functional Verification of a RISC-V Vector Accelerator

[14] Bug-finding results Functional Verification of a RISC-V Vector Accelerator

[15] Regression strategy Functional Verification of a RISC-V Vector Accelerator

[16] MAB coverage closure UVM-based verification of RISC-V superscalar processors

[17] MAB virtual sequences UVM-based verification of RISC-V superscalar processors