UVM
ToolUVM, in the provided evidence, refers to the Universal Verification Methodology used to build modular, scalable, reusable SystemVerilog verification environments. Cited works describe UVM environments built with agents, sequencers, drivers, monitors, scoreboards, and reference-model comparison for verifying RTL designs such as RISC-V vector accelerators and multi-hart CPUs, often combined with RISCV-DV, Spike, SystemVerilog Assertions, and CI regressions, and driving coverage closure via techniques such as Multi-Armed Bandit (MAB) decision making.
First seen 5/27/2026
Last seen 7/19/2026
Evidence 29 chunks
Wiki v4
WIKI
Overview
UVM is used in the evidence as the Universal Verification Methodology for building a modular, scalable, and reusable verification environment. The cited RISC-V vector-accelerator paper references the Accellera UVM standard and states that UVM was selected because the verification tools had to be shareable with partners and reusable for next-generation designs. [UVM role]
In that case study, the design under test was a RISC-V based decoupled Vector Processing Unit (VPU) connected to a scalar processor core through the Open Vector Interface (OVI). The verification infrastructure consisted of a UVM environment, step-by-step co-simulation of vector instructions using Spike as a reference model, automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. [VPU verification infrastructure]
NEIGHBORHOOD
4 nodes · 4 edgesgraph · UVM · depth=1
RELATIONSHIPS
28 connectionsUVM implements constrained random verification through its library and methodology.
UVM is a standard methodology tool used for functional verification of processors.
The UVM testbench is used for verifying the RTL design of the vector accelerator.
The paper describes a verification approach built on the UVM methodology.
The UVM environment includes a scoreboard that compares VPU results with reference model results.
UVM test platforms are maintained by major processor vendors for processor verification.
The UVM environment implements a functional coverage plan to measure verification completeness.
SystemVerilog Assertions are used alongside the UVM testbench to improve observability and detect bugs.
The UVM environment uses Spike as its reference model for co-simulation.
RISCV-DV is used within the UVM verification flow to generate random test programs.
The UVM environment performs step-by-step co-simulation of all vector instructions with Spike.
The UVM environment is used to functionally verify the VPU.
UVM is based on SystemVerilog libraries and standard.
UVM is used to verify RTL designs
UVM is commonly used for stimulus generation in verification flows
CPU verification methodologies often employ UVM
RISCV-DV experiments were run using the UVM framework.
The UVM environment uses one agent for each OVI sub-interface.
Virtual sequences are used in the UVM environment to coordinate stimulus across sub-interfaces.
UVM is a good framework for constrained-random instruction generation.
UVM implements coverage-driven verification as a standard methodology for reusable testbench structures.
UVM is used as the framework for simulation-based verification.
UVM is a class library defined using the syntax and semantics of SystemVerilog.
UVM-based verification uses functional coverage as a quality metric.
The UVM-based verification flow uses constrained random verification test sequences.
UVM is used as the standard for simulation-based verification.
UVM implements random instruction generation for processor verification.
CRV approach is implemented using UVM with SystemVerilog.
LINKED ENTITIES
6 linksStimulus Generation USES Extracted graph relationship
RTL USES Extracted graph relationship
CPU Verification USES Extracted graph relationship
riscv-dv USED_WITH The evidence explicitly describes RISCV-DV as a SystemVerilog/UVM-based RISC-V instruction generator used together with the UVM framework in both the RISC-V vector-accelerator case study and HARTBREAKER.
spike USED_WITH The evidence describes Spike being used as the golden/reference model inside UVM environments for VPU verification and as a deterministic ISS for store values in HARTBREAKER's UVM-based experiments.
HARTBREAKER USED_WITH The evidence describes HARTBREAKER's RISCV-DV-driven experiments being run using the UVM framework with a commercial simulator, targeting Rocket, BOOM, Toooba, NaxRiscv, and XiangShan.
CITATIONS
9 sources9 citations — click to expand
[1] UVM was selected in the cited RISC-V vector-accelerator work because the verification tools had to be shareable with partners and reusable for next-generation designs. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[2] The cited RISC-V vector-accelerator paper describes a UVM environment with one agent per OVI sub-interface, each containing a sequencer, driver, and monitor connected to a virtual interface. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[3] Virtual sequences synchronized sub-interfaces in the VPU UVM environment using UVM events and triggers, and the authors noted that splitting stimulus across multiple agents complicated maintenance and extension. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[4] The cited work modified Spike so that SystemVerilog could call it through DPI to act as a golden/reference model for UVM scoreboard comparison, with a special C reference model for unordered floating-point reductions. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[5] RISCV-DV is described in the evidence as a SystemVerilog/UVM-based open-source RISC-V instruction generator developed by Google and adapted to RVV 0.7.1 in the cited VPU case study, with progressive removal of blacklisted instructions. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[6] The cited project reported 3005 errors found, 95.79% average functional coverage, 72.64% average code coverage (90.90% statement, 49.83% toggle), with nightly regressions growing from 24 to 50 tests and daily regressions running about 600 tests. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[7] A separate UVM-based source describes Multi-Armed Bandit decision making for autonomous coverage closure, where test sequences are treated as slot-machine arms and a virtual sequence is defined as a collection of test sequences that drive each DUT interface. IEEE Xplore Full-Text PDF (c4f63828-c2fd-4d88-966a-8fcabe80b769)
[8] HARTBREAKER used Verilator to simulate designs and Spike as a golden model; its RISCV-DV experiments were run using the UVM framework with a commercial simulator on Rocket, BOOM, Toooba, NaxRiscv, and XiangShan. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs (ISCA'26)
[9] A reinforcement-learning RISC-V functional-verification thesis describes a UVM testbench with an interactive driver, transaction-level UVM transport ports, byte-addressable data memory and instruction memory loaded from a .vmem file, and a monitor that observes only data-memory interface signals and triggers end-of-program via a Spike-written address before transitioning to the UVM check phase. Reinforcement Learning Framework for RISC-V Functional Verification