SystemVerilog Assertions

Technique

SystemVerilog Assertions (SVA) are used as an assertion-based verification technique to check expected hardware-interface behavior and improve observability during simulation. In the cited RISC-V vector accelerator verification work, more than 50 SVAs were written against the Open Vector Interface specifications, with emphasis on memory-related sub-interfaces; they helped identify both VPU design bugs and UVM stimulation issues, and their active/passed status was tracked in CI coverage runs.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

SystemVerilog Assertions (SVA) are described in the evidence as a verification technique used to check that a hardware interface behaves as expected. In the cited RISC-V vector accelerator verification environment, the verification team wrote SVAs against the Open Vector Interface (OVI) specifications for the Vector Processing Unit (VPU), implementing more than 50 assertions.

Role in verification

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RELATIONSHIPS

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UVM ← uses 93% 2e

SystemVerilog Assertions are used alongside the UVM testbench to improve observability and detect bugs.

Functional Verification of a RISC-V Vector Accelerator ← uses 95% 2e

SystemVerilog Assertions are used to check OVI protocol compliance and detect bugs.

LINKED ENTITIES

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UVM USES Extracted graph relationship

Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] SystemVerilog Assertions were used to check that the VPU interface behaved as expected against the OVI specifications, with more than 50 implemented. Functional Verification of a RISC-V Vector Accelerator

[2] During early UVM testbench development, the SVAs helped identify VPU bugs and problems in UVM stimulation. Functional Verification of a RISC-V Vector Accelerator

[3] Most asserted properties targeted memory-related sub-interfaces and were used to ensure OVI specifications were followed throughout the project. Functional Verification of a RISC-V Vector Accelerator

[4] Assertions were added to improve observability because instruction-result mismatches may not identify the cause of an error. Functional Verification of a RISC-V Vector Accelerator

[5] The verification environment used UVM and a scoreboard with Spike co-simulation as a reference model. Functional Verification of a RISC-V Vector Accelerator

[6] Assertion usage, including active and passed assertions, was recorded together with functional and code coverage in CI simulation runs. Functional Verification of a RISC-V Vector Accelerator

[7] The OVI interface included ISSUE, DISPATCH, COMPLETED, MEMOP, LOAD, STORE, and MASK-INDEX sub-interfaces; ISSUE, STORE, and MASK-INDEX used a credit system for handshaking. Functional Verification of a RISC-V Vector Accelerator

[8] The bibliography of the cited work references Cerny et al., SVA: The Power of Assertions. Functional Verification of a RISC-V Vector Accelerator