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SystemVerilog Assertions

Technique WIKI v1 · 5/28/2026

SystemVerilog Assertions (SVA) are used as an assertion-based verification technique to check expected hardware-interface behavior and improve observability during simulation. In the cited RISC-V vector accelerator verification work, more than 50 SVAs were written against the Open Vector Interface specifications, with emphasis on memory-related sub-interfaces; they helped identify both VPU design bugs and UVM stimulation issues, and their active/passed status was tracked in CI coverage runs.

Overview

SystemVerilog Assertions (SVA) are described in the evidence as a verification technique used to check that a hardware interface behaves as expected. In the cited RISC-V vector accelerator verification environment, the verification team wrote SVAs against the Open Vector Interface (OVI) specifications for the Vector Processing Unit (VPU), implementing more than 50 assertions.

Role in verification

The cited work used a UVM-based environment with a scoreboard and a Spike co-simulation reference model to detect instruction-result mismatches. The authors noted that a mismatch is important but may not identify the root cause, so they added SystemVerilog assertions to improve observability.

In the assertions section of the same work, the VPU interface is identified as a critical point. The team therefore reviewed the OVI specifications and wrote SVAs to check that the interface behaved as expected. During the early stages of UVM testbench development, these assertions helped identify both VPU bugs and problems in UVM stimulation.

Targeted checks

Most of the asserted properties in the RISC-V vector accelerator case study targeted memory-related sub-interfaces. Their purpose was to ensure that the OVI specifications were strictly followed throughout the project.

The broader OVI interface in that environment included multiple sub-interfaces, such as ISSUE, DISPATCH, COMPLETED, MEMOP, LOAD, STORE, and MASK-INDEX. The evidence also notes that ISSUE, STORE, and MASK-INDEX used a credit system for handshaking between the VPU and scalar core, illustrating why interface-level protocol checks were important.

Use with coverage and CI

The same verification effort tracked assertion usage, specifically active and passed assertions, alongside functional coverage and code coverage. These metrics were collected from simulations run by the continuous-integration infrastructure, which generated and ran tests and collected coverage metrics.

Related entities

  • UVM: The cited environment was UVM-based, and SVAs were used during UVM testbench development to find VPU bugs and UVM stimulation problems.
  • Functional Verification of a RISC-V Vector Accelerator: The paper reports the use of more than 50 SVAs in a RISC-V vector accelerator verification environment.

LINKED ENTITIES

2 links
UVM USES
Functional Verification of a RISC-V Vector Accelerator USES

CITATIONS

8 sources
8 citations
[1] SystemVerilog Assertions were used to check that the VPU interface behaved as expected against the OVI specifications, with more than 50 implemented. Functional Verification of a RISC-V Vector Accelerator
[2] During early UVM testbench development, the SVAs helped identify VPU bugs and problems in UVM stimulation. Functional Verification of a RISC-V Vector Accelerator
[3] Most asserted properties targeted memory-related sub-interfaces and were used to ensure OVI specifications were followed throughout the project. Functional Verification of a RISC-V Vector Accelerator
[4] Assertions were added to improve observability because instruction-result mismatches may not identify the cause of an error. Functional Verification of a RISC-V Vector Accelerator
[5] The verification environment used UVM and a scoreboard with Spike co-simulation as a reference model. Functional Verification of a RISC-V Vector Accelerator
[6] Assertion usage, including active and passed assertions, was recorded together with functional and code coverage in CI simulation runs. Functional Verification of a RISC-V Vector Accelerator
[7] The OVI interface included ISSUE, DISPATCH, COMPLETED, MEMOP, LOAD, STORE, and MASK-INDEX sub-interfaces; ISSUE, STORE, and MASK-INDEX used a credit system for handshaking. Functional Verification of a RISC-V Vector Accelerator
[8] The bibliography of the cited work references Cerny et al., SVA: The Power of Assertions. Functional Verification of a RISC-V Vector Accelerator