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UVM

Tool WIKI v3 · 5/28/2026

UVM, in the provided evidence, refers to the Universal Verification Methodology used to build modular, scalable, reusable SystemVerilog verification environments. The cited RISC-V vector-accelerator work used a UVM environment with agents, virtual sequences, a scoreboard, Spike co-simulation, RISCV-DV constrained-random binaries, SystemVerilog Assertions, CI regressions, and functional coverage, reporting 3005 errors found and 95.79% functional coverage.

Overview

UVM is used in the evidence as the Universal Verification Methodology for building a modular, scalable, and reusable verification environment. The cited RISC-V vector-accelerator paper references the Accellera UVM standard and states that UVM was selected because the verification tools had to be shareable with partners and reusable for next-generation designs. [UVM role]

In that case study, the design under test was a RISC-V based decoupled Vector Processing Unit (VPU) connected to a scalar processor core through the Open Vector Interface (OVI). The verification infrastructure consisted of a UVM environment, step-by-step co-simulation of vector instructions using Spike as a reference model, automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. [VPU verification infrastructure]

Testbench organization

The UVM environment described in the evidence used a UVM top module that instantiated the UVM environment. Because the OVI/VPU interface was split into several semi-independent sub-interfaces, the authors created one UVM agent per sub-interface. For example, the issue sub-interface had an agent containing a sequencer, a driver, and a monitor connected to a virtual interface. [Agent structure]

Virtual sequences created interface-specific transactions and sent them to the corresponding interface. Drivers stimulated their sub-interfaces using transaction values, while monitors captured interface state and sent information back through the sequencer so that virtual sequences could react and produce new stimulus. Because the sub-interfaces were interdependent, the implementation used UVM events to transmit data along with event triggers and synchronize communication among virtual sequences. [Virtual sequences and synchronization]

The evidence also records a design lesson: implementing communication across several agents complicated maintenance, extension, and performance. The authors proposed that a future environment could use a single stimulus-producing agent to simplify sub-interface communication and expansion. [Agent-maintenance lesson]

Scoreboard and co-simulation

The environment used a UVM scoreboard to compare VPU results against a reference model. Spike, the RISC-V ISA simulator, was used for co-simulation and served two roles: it executed scalar instructions while providing vector instructions to UVM in program order, and it acted as a golden/reference model for checking DUT results. [Scoreboard and Spike]

The authors modified Spike so that SystemVerilog could call it through DPI functions, resume simulation until a vector instruction executed, return reference results to UVM, read Spike memory, and handle selected RISC-V Vector 0.7.1 requirements. When Spike found a vector instruction, the instruction, expected results, and relevant data were packed as a transaction and sent to the issue agent; after VPU execution, the VPU results were compared with the reference results. [Spike integration]

The paper notes a special case for unordered floating-point reductions: Spike and the VPU could legally use different reduction algorithms, which could create apparent mismatches and leave divergent values in Spike vector registers. The authors handled this by adding an independent C reference model for those reductions and injecting matching results back into Spike when appropriate. [Reduction reference-model exception]

Stimulus generation with RISCV-DV

RISCV-DV is described in the evidence as a SystemVerilog/UVM-based open-source RISC-V instruction generator developed by Google. The case study used RISCV-DV to generate random RISC-V assembly tests and provide vector instructions for VPU verification. Because RISCV-DV targeted a later RISC-V Vector version than 0.7.1, the authors adapted it for the design, including generation of vsetvli instructions, memory-operation changes for element width and vector length, data-page initialization options, memory-address constraints to avoid exceptions, and adaptation to RVV 0.7.1. [RISCV-DV role]

During development, some instructions were initially blacklisted because design modules were incomplete. As errors were fixed, instructions were gradually removed from the blacklist until all implemented instructions were enabled. [RISCV-DV blacklisting]

Assertions and coverage

The verification environment used SystemVerilog Assertions for the OVI interface. The authors implemented more than 50 assertions, mainly targeting memory-related sub-interfaces, to check that OVI behavior followed the specification. These assertions helped identify both VPU bugs and problems in UVM stimulation early in testbench development. [Assertions]

The authors also defined and implemented a functional coverage plan. Coverage focused on directly observable VPU-interface behavior such as instructions, execution parameters, and values in memory sub-interfaces, as well as selected internal-module metrics. The environment included ISA tests for key instruction configurations and RISCV-DV random tests for additional stress. [Functional coverage plan]

Reported coverage results included an average functional coverage of 95.79% across design units and average code coverage of 72.64%, including 90.90% statement coverage and 49.83% toggle coverage. The authors noted that lower code coverage reflected cases that were difficult to drive in the environment and could also indicate unused data structures or conditions in the RTL. [Coverage results]

Regression and bug-finding results

The cited project used automated constrained-random test generation, simulation, error reporting, and CI/CD infrastructure. During the reported process, the team found 3005 errors and reached 95.79% functional coverage. [Bug-finding results]

The test strategy included nightly and daily regressions. Night runs increased from 24 tests per night between April and July to 50 tests between August and the end of November before RTL freeze; each test contained approximately 500 vector instructions. Later pipelines ran about 600 tests every day for coverage collection and bug finding while VPU development continued. [Regression strategy]

Automated coverage-closure context

A separate UVM-based source in the evidence describes Multi-Armed Bandit (MAB) decision making for autonomous coverage closure. In that formulation, test sequences are treated like slot-machine arms: each sequence is applied to the DUT for a number of cycles, a reward is recorded based on coverage performance, and the MAB policy recommends the next sequence while balancing exploitation of sequences that have improved coverage with exploration of other sequences. [MAB coverage closure]

That same source defines a virtual sequence as a collection of test sequences that drive each DUT interface. It states that, in the proposed MAB framework, the set of virtual sequences and their internal sequences are fixed beforehand, and parameters are pre-selected through representative random sampling so repeated execution can let the MAB learn each sequence's coverage performance. [MAB virtual sequences]

Practical interpretation

Within the provided evidence, UVM is best understood as a reusable verification-methodology framework for organizing simulation infrastructure around agents, virtual sequences, monitors, scoreboards, reference-model comparison, assertions, and coverage collection. The RISC-V vector-accelerator case study shows UVM used together with Spike, RISCV-DV, SystemVerilog Assertions, and CI regressions to verify RTL and drive coverage closure.

LINKED ENTITIES

11 links
Co-simulation IMPLEMENTS
UVM scoreboard IMPLEMENTS
UVM agent IMPLEMENTS
virtual sequence IMPLEMENTS
Functional Coverage IMPLEMENTS
SystemVerilog Assertions USES
spike USES
riscv-dv USES
Vector Processing Unit (VPU) EVALUATES
RTL EVALUATES
Functional Verification of a RISC-V Vector Accelerator USES

CITATIONS

17 sources
17 citations
[1] UVM role Functional Verification of a RISC-V Vector Accelerator
[2] VPU verification infrastructure Functional Verification of a RISC-V Vector Accelerator
[3] Agent structure Functional Verification of a RISC-V Vector Accelerator
[4] Virtual sequences and synchronization Functional Verification of a RISC-V Vector Accelerator
[5] Agent-maintenance lesson Functional Verification of a RISC-V Vector Accelerator
[6] Scoreboard and Spike Functional Verification of a RISC-V Vector Accelerator
[7] Spike integration Functional Verification of a RISC-V Vector Accelerator
[8] Reduction reference-model exception Functional Verification of a RISC-V Vector Accelerator
[9] RISCV-DV role Functional Verification of a RISC-V Vector Accelerator
[10] RISCV-DV blacklisting Functional Verification of a RISC-V Vector Accelerator
[11] Assertions Functional Verification of a RISC-V Vector Accelerator
[12] Functional coverage plan Functional Verification of a RISC-V Vector Accelerator
[13] Coverage results Functional Verification of a RISC-V Vector Accelerator
[14] Bug-finding results Functional Verification of a RISC-V Vector Accelerator
[15] Regression strategy Functional Verification of a RISC-V Vector Accelerator
[16] MAB coverage closure UVM-based verification of RISC-V superscalar processors
[17] MAB virtual sequences UVM-based verification of RISC-V superscalar processors

VERSION HISTORY

v3 · 5/28/2026 · gpt-5.5 (current)
v2 · 5/28/2026 · gpt-5.5
v1 · 5/27/2026 · gpt-5.5