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Vector Processing Unit (VPU)

Concept

The Vector Processing Unit (VPU) is an academic RISC-V-based decoupled vector accelerator developed in the European Processor Initiative context by Barcelona Supercomputing Center. It implements RISC-V Vector extension 0.7.1, connects to a scalar RISC-V core through the Open Vector Interface, and was functionally verified using a UVM-based co-simulation environment with Spike as a reference model.

First seen 5/27/2026
Last seen 5/28/2026
Evidence 10 chunks
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WIKI

Overview

The Vector Processing Unit (VPU) is an academic RISC-V-based decoupled vector accelerator developed in the context of the European Processor Initiative (EPI). The cited verification work states that the accelerator was successfully taped out, implemented version 0.7.1 of the RISC-V Vector extension (RVV), and was connected to a scalar processor core through the Open Vector Interface (OVI). [VPU identity and context]

Within the EPI project, Barcelona Supercomputing Center developed the vector accelerator, SemiDynamics designed the scalar RISC-V core, EXTOLL handled top-level test-chip integration, and Fraunhofer coordinated tape-out. [EPI development roles]

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections
Open Vector Interface (OVI) uses → 99% 6e
The VPU is connected to the scalar core via the Open Vector Interface.
Functional Verification of a RISC-V Vector Accelerator ← evaluates 99% 5e
The paper presents the functional verification of a RISC-V vector accelerator (VPU).
UVM ← evaluates 97% 2e
The UVM environment is used to functionally verify the VPU.
European Processor Initiative part of → 93% 2e
The VPU was developed as part of the European Processor Initiative project.
Barcelona Supercomputing Center ← introduces 97% 2e
BSC developed the vector accelerator (VPU) as part of the EPI project.
Open Vector Interface (OVI) ← part of 92% 1e
OVI is the interface through which the VPU connects to the scalar core

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator EVALUATES Extracted graph relationship
Open Vector Interface (OVI) USES Extracted graph relationship
Barcelona Supercomputing Center INTRODUCES Extracted graph relationship

CITATIONS

25 sources
25 citations — click to expand
[1] VPU identity and context Functional Verification of a RISC-V Vector Accelerator
[2] EPI development roles Functional Verification of a RISC-V Vector Accelerator
[3] VPU architecture Functional Verification of a RISC-V Vector Accelerator
[4] VPU compute capabilities Functional Verification of a RISC-V Vector Accelerator
[5] VPU scalar-core integration Functional Verification of a RISC-V Vector Accelerator
[6] VPU memory behavior Functional Verification of a RISC-V Vector Accelerator
[7] OVI sub-interfaces Functional Verification of a RISC-V Vector Accelerator
[8] OVI sub-interface roles Functional Verification of a RISC-V Vector Accelerator
[9] OVI handshaking and instruction effects Functional Verification of a RISC-V Vector Accelerator
[10] UVM verification strategy Functional Verification of a RISC-V Vector Accelerator
[11] UVM environment structure Functional Verification of a RISC-V Vector Accelerator
[12] Constrained-random strategy Functional Verification of a RISC-V Vector Accelerator
[13] Spike roles Functional Verification of a RISC-V Vector Accelerator
[14] Spike modifications Functional Verification of a RISC-V Vector Accelerator
[15] Scoreboard comparison Functional Verification of a RISC-V Vector Accelerator
[16] Floating-point reduction handling Functional Verification of a RISC-V Vector Accelerator
[17] RISCV-DV use Functional Verification of a RISC-V Vector Accelerator
[18] RISCV-DV adaptations Functional Verification of a RISC-V Vector Accelerator
[19] OVI assertions Functional Verification of a RISC-V Vector Accelerator
[20] CI pipelines Functional Verification of a RISC-V Vector Accelerator
[21] Verification results Functional Verification of a RISC-V Vector Accelerator
[22] Memory verification complexity Functional Verification of a RISC-V Vector Accelerator
[23] Memory operation checking Functional Verification of a RISC-V Vector Accelerator
[24] Masked memory checking Functional Verification of a RISC-V Vector Accelerator
[25] OVI retries Functional Verification of a RISC-V Vector Accelerator