Constrained Random Verification

Technique

Constrained Random Verification (CRV) is a stimulus-generation technique used in hardware design verification in which random inputs are sampled subject to protocol or design constraints so that only legal actions are produced. The provided evidence portrays CRV as an established baseline in chip-design verification studies (sampling uniformly over legal actions per cycle, enforcing legality by construction, and used within coverage-driven simulation flows such as UVM-based verification), as a conventional method whose coverage limitations motivate newer approaches such as coverage-guided fuzzing and reinforcement-learning-based stimulus generation, and as the subject of dedicated RISC-V verification studies. New evidence also documents a formal, uniformity-guaranteed CRV sampler (TraceSampler) that addresses the lack of distribution guarantees in conventional CRV, and a Python-based PyUVM/PyVSC verification environment that targets constrained randomization and functional coverage. Evidence-supported descriptions of CRV focus on its role and comparative positioning rather than internal algorithmic details.

First seen 5/26/2026

Last seen 7/17/2026

Evidence 26 chunks

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Constrained Random Verification

Overview

Constrained Random Verification (CRV) is a constrained-random or constraint-based testcase-generation technique used in hardware design verification. In the evidence available, CRV is described as a stimulus generator that "samples uniformly over the subset of legal actions at each cycle, modeling typical constrained-random stimulus," and is used as one of several compared stimulus-generation methods in recent chip-verification studies. [crv-stimulusrl]

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RELATIONSHIPS

21 connections

UVM ← implements 94% 3e

UVM implements constrained random verification through its library and methodology.

SystemVerilog uses → 95% 2e

SystemVerilog is the language used to implement CRV with UVM.

StimulusRL compares with → 100% 2e

StimulusRL is compared against constrained-random verification as a baseline.

Boolean CNF Formula uses → 85% 2e

CRV uses Boolean constraints (typically encoded as CNF) to generate test vectors.

UniGen uses → 95% 2e

UniGen is intended to be used in constrained-random verification for generating test vectors.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← compares with 85% 2e

The paper discusses constrained random verification as a complementary technique.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← evaluates 95% 1e

Provides an overview and evaluation of constrained random verification techniques.

UVM uses → 95% 1e

CRV approach is implemented using UVM with SystemVerilog.

MIPS Processor evaluates → 93% 1e

CRV approach with UVM was used to verify a MIPS processor.

Aldec Riviera-PRO uses → 93% 1e

The CRV functional coverage verification was run using Aldec Riviera Pro tool.

coverage driven simulation ← uses 93% 1e

Coverage driven simulation is based on UVM constrained random methods.

RTL model uses → 90% 1e

CRV involves simulating a gate-level or RTL model with specific input patterns.

Test Vector Generation uses → 95% 1e

CRV depends on generating random test vectors satisfying constraints.

Simulation-based Functional Verification uses → 95% 1e

CRV is a form of simulation-based functional verification.

Markov Chain Monte Carlo Sampling uses → 80% 1e

MCMC adaptations have been used for constrained-random verification.

Hardware fuzzing ← compares with 85% 1e

Constrained Random Verification is contrasted with hardware fuzzing as a traditional verification methodology.

Processor Verification ← uses 92% 1e

Constrained random verification is used in processor verification to achieve good coverage.

VMM uses → 92% 1e

The CRV approach leverages commercially available base classes from VMM.

Object-Oriented Stimulus Generation ← implements 90% 1e

The object-oriented approach implements constrained-random verification for processor testing.

Design Under Test evaluates → 92% 1e

Constrained-random verification is applied to evaluate the processor design under test.

Instruction Set Architecture uses → 88% 1e

CRV requires knowledge of the processor's instruction set architecture to generate effective stimuli.

LINKED ENTITIES

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coverage driven simulation USES Extracted graph relationship

CITATIONS

12 sources

12 citations — click to expand

[1] CRV samples uniformly over the subset of legal actions at each cycle, modeling typical constrained-random stimulus. StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification

[2] CRV and StimulusRL enforce legality and therefore converge to 36/38 bins (0.947) on FIFO8 because the coverage model includes two explicit illegal-operation attempt bins. StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification

[3] CRV in the compared taxonomy of stimulus generators uses legality constraints but neither coverage feedback nor a learned policy. StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification

[4] On DMCache, a 2000-step CRV run takes 0.537 ± 0.004 s, compared with 0.378 ± 0.004 s for Random and 2.111 ± 0.005 s for StimulusRL. StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification

[5] Conventional verification approaches, such as random and constrained-random verification, struggle to achieve adequate coverage of the vast state space in modern SoCs, and even millions of random or constrained-random test vectors fail to activate a majority of complex execution paths. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution

[6] Complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard. Universal Verification Methodology Coverage for Bluespec RISC-V Cores

[7] A Python-based verification environment for constrained random verification uses PyUVM (Python-based UVM 1.2 implementation) and PyVSC (facilitating constrained randomization and functional coverage), and is compared against SystemVerilog-UVM methodology. Towards Efficient Design Verification -- Constrained Random Verification using PyUVM

[8] Conventional CRV solutions provide no formal guarantees on the distribution of generated runs; TraceSampler uses Algebraic Decision Diagrams to sample bounded traces of a sequential circuit with provable uniformity (or bias) guarantees while satisfying given constraints. On Uniformly Sampling Traces of a Transition System (Extended Version)

[9] A RISC-V test-sequence generation paper cites Ahmadi-Pour, Herdt, and Drechsler, Constrained random verification for RISC-V: Overview, evaluation and discussion, MBMV 2021, 24th Workshop, 2021, pages 1–8. A RISC-V Test Sequences Generation Method Based on Instruction ...

[10] Coverage-guided fuzzing for ISS verification uses LLVM libFuzzer with a functional coverage metric that complements code coverage and a mutation procedure tailored to ISS verification. A RISC-V Test Sequences Generation Method Based on Instruction ...

[11] The coverage-guided fuzzing case study on three RISC-V ISSs was effective at maximizing most coverage metrics and found new errors in every considered ISS, including an error in the official RISC-V reference simulator Spike. A RISC-V Test Sequences Generation Method Based on Instruction ...

[12] Coverage-guided fuzzing is useful for triggering and checking corner cases and error cases and can complement other testcase generation techniques, with references including constraint-based and constrained-random verification work. A RISC-V Test Sequences Generation Method Based on Instruction ...