Constrained Random Verification

Technique

Constrained Random Verification (CRV) is a constrained-random stimulus-generation technique used in hardware design verification, in which random inputs are sampled subject to protocol or design constraints so that only legal actions are produced. The provided evidence portrays CRV as a baseline technique in chip-design verification studies (sampling uniformly over legal actions per cycle, enforcing legality by construction, and used within coverage-driven simulation flows such as UVM-based verification and RISC-V instruction stream generators like riscv-dv), as a conventional method whose coverage limitations motivate newer approaches such as coverage-guided fuzzing and reinforcement-learning-based stimulus generation, and as the subject of dedicated RISC-V verification studies. New evidence also documents a broader landscape of uniformity-aware CRV samplers, including SAT-witness generators that adapt MCMC, BDD, hashing, and interval-propagation techniques to constrained-random verification, with heuristic variants preserving scalability but sacrificing theoretical guarantees, and PyUVM/PyVSC-based Python verification environments targeting constrained randomization and functional coverage.

First seen 5/26/2026

Last seen 9/28/2026

Evidence 30 chunks

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WIKI

Constrained Random Verification

Overview

Constrained Random Verification (CRV) is a constrained-random or constraint-based testcase-generation technique used in hardware design verification. In the evidence available, CRV is described as a stimulus generator that "samples uniformly over the subset of legal actions at each cycle, modeling typical constrained-random stimulus," and is used as one of several compared stimulus-generation methods in recent chip-verification studies. [crv-stimulusrl]

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NEIGHBORHOOD

2 nodes · 2 edges

graph · constrained random verification · depth=1

RELATIONSHIPS

27 connections

UVM ← implements 94% 3e

UVM implements constrained random verification through its library and methodology.

StimulusRL compares with → 100% 2e

StimulusRL is compared against constrained-random verification as a baseline.

Boolean CNF Formula uses → 85% 2e

CRV uses Boolean constraints (typically encoded as CNF) to generate test vectors.

UniGen uses → 95% 2e

UniGen is intended to be used in constrained-random verification for generating test vectors.

SystemVerilog uses → 95% 2e

SystemVerilog is the language used to implement CRV with UVM.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← compares with 85% 2e

The paper discusses constrained random verification as a complementary technique.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← evaluates 95% 1e

Provides an overview and evaluation of constrained random verification techniques.

UVM uses → 95% 1e

CRV approach is implemented using UVM with SystemVerilog.

MIPS Processor evaluates → 93% 1e

CRV approach with UVM was used to verify a MIPS processor.

Aldec Riviera-PRO uses → 93% 1e

The CRV functional coverage verification was run using Aldec Riviera Pro tool.

coverage driven simulation ← uses 93% 1e

Coverage driven simulation is based on UVM constrained random methods.

RTL model uses → 90% 1e

CRV involves simulating a gate-level or RTL model with specific input patterns.

Test Vector Generation uses → 95% 1e

CRV depends on generating random test vectors satisfying constraints.

Simulation-based Functional Verification uses → 95% 1e

CRV is a form of simulation-based functional verification.

Markov Chain Monte Carlo Sampling uses → 80% 1e

MCMC adaptations have been used for constrained-random verification.

Hardware fuzzing ← compares with 85% 1e

Constrained Random Verification is contrasted with hardware fuzzing as a traditional verification methodology.

uniform SAT witness generation uses → 97% 1e

CRV requires sampling solutions uniformly or almost-uniformly at random to discover bugs.

Boolean Satisfiability uses → 95% 1e

CRV constraints are encoded as Boolean formulae for SAT-based witness generation.

RTL Simulation uses → 92% 1e

CRV operates by simulating gate-level or RTL models of circuits.

almost-uniform generation uses → 95% 1e

CRV requires almost-uniform or uniform sampling of constraint solutions for unbiased bug discovery.

Markov Chain Monte Carlo sampling uses → 88% 1e

MCMC methods have been adapted for use in constrained-random verification for sampling solutions.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← uses 93% 1e

The title explicitly states the technique discussed and evaluated is constrained random verification.

Processor Verification ← uses 92% 1e

Constrained random verification is used in processor verification to achieve good coverage.

VMM uses → 92% 1e

The CRV approach leverages commercially available base classes from VMM.

Object-Oriented Stimulus Generation ← implements 90% 1e

The object-oriented approach implements constrained-random verification for processor testing.

Design Under Test evaluates → 92% 1e

Constrained-random verification is applied to evaluate the processor design under test.

Instruction Set Architecture uses → 88% 1e

CRV requires knowledge of the processor's instruction set architecture to generate effective stimuli.

LINKED ENTITIES

1 links

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion USES Extracted graph relationship

CITATIONS

15 sources

15 citations — click to expand

[1] CRV samples uniformly over the subset of legal actions at each cycle, modeling typical constrained-random stimulus. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen (referenced StimulusRL/arXiv 2407.10317 source)

[2] On DMCache, a 2000-step CRV run takes 0.537 ± 0.004 s, compared with 0.378 ± 0.004 s for Random and 2.111 ± 0.005 s for StimulusRL. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen (referenced StimulusRL/arXiv 2407.10317 source)

[3] Even millions of random or constrained-random test vectors fail to activate a majority of complex execution paths in modern SoCs. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen (referenced FuSS source)

[4] A Python-based verification environment for constrained random verification is built on PyUVM and PyVSC and is compared against SystemVerilog-UVM methodology. Towards Efficient Design Verification -- Constrained Random Verification using PyUVM

[5] TraceSampler uses Algebraic Decision Diagrams to sample bounded traces of a sequential circuit with provable uniformity (or bounded bias) guarantees while satisfying given constraints. On Uniformly Sampling Traces of a Transition System (Extended Version)

[6] The MBMV 2021 paper 'Constrained random verification for RISC-V: overview, evaluation and discussion' by Ahmadi-Pour, Herdt, and Drechsler places CRV in the RISC-V verification literature. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen

[7] Industry reporting describes coverage driven simulation based on UVM constrained random methods for RISC-V, using the Google RISCV-DV open-source project. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen (referenced SemiEngineering source)

[8] Coverage-guided fuzzing (CGF) implemented on LLVM libFuzzer with a functional coverage metric can complement other testcase generation techniques and found new errors in RISC-V ISSs including Spike. Liste der Publikationen im Scale4Edge Projekt der Universität Bremen (referenced CGF-ISS source)

[9] Prior CRV sampling work has either sacrificed scalability for uniformity guarantees or sacrificed uniformity guarantees for scalability, and bridging the two extremes is an open research direction. Balancing Scalability and Uniformity in SAT Witness Generator

[10] BDD-based SAT-witness sampling provides uniform sampling but suffers from scalability problems; adapted BDD-based techniques sacrifice uniformity guarantees for scalability. Balancing Scalability and Uniformity in SAT Witness Generator

[11] Random seeding of DPLL SAT solvers offers strong performance, but the resulting witness distributions can be highly skewed. Balancing Scalability and Uniformity in SAT Witness Generator

[12] MCMC-based adaptations for constrained-random verification exist but are heuristic and do not preserve theoretical guarantees of uniformity; convergence is often impractically slow. Balancing Scalability and Uniformity in SAT Witness Generator

[13] Interval-propagation and belief-network samplers scale well but their distributions can deviate significantly from the uniform distribution. Balancing Scalability and Uniformity in SAT Witness Generator

[14] Hashing-based sampling partitions the witness space into roughly equal-sized cells using r-wise independent hash functions; XORSample' uses 3-wise independent linear hash functions, and UniWit (Chakraborty, Meel, and Vardi) extends this approach toward marrying scalability with uniformity. Balancing Scalability and Uniformity in SAT Witness Generator

[15] A RISC-V Summit 2022 tutorial lists constrained random testing alongside ISS-based trace compare, UVM functional coverage, RVVI, interrupts, signatures, and instruction stream generators such as riscv-dv and Valtrix STING, and notes that RISC-V processor verification has historically used proprietary techniques without industry-standard best practices or verification IP. An introduction to RISC-V processor verification techniques