Coverage-Driven Simulation

Technique

Coverage-driven simulation is a functional verification methodology that combines constrained-random stimulus generation with feedback from coverage metrics to systematically close verification gaps. In the RISC-V ecosystem, it is typically implemented on top of the Universal Verification Methodology (UVM) standard, using open-source instruction-stream generators such as Google RISC-V-DV together with Synopsys verification solutions to track functional coverage of a core.

First seen 7/4/2026

Last seen 7/4/2026

Evidence 1 chunks

Wiki v1

WIKI

Coverage-Driven Simulation

Definition

Coverage-driven simulation is a verification methodology in which the stimulus applied to a design under test (DUT) and the checks performed against it are guided by coverage metrics. Rather than relying solely on hand-written directed tests, random or constrained-random stimulus is generated, executed against the DUT, and the resulting behavior is measured against a coverage model that encodes the design's intended features, corner cases, and architectural states.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

3 connections

RISC-V verification ← uses 95% 1e

RISC-V verification employs coverage driven simulation as one of its methodologies.

constrained random verification uses → 93% 1e

Coverage driven simulation is based on UVM constrained random methods.

Universal Verification Methodology implements → 92% 1e

Coverage driven simulation is compliant with the Universal Verification Methodology standard.

LINKED ENTITIES

3 links

RISC-V verification USES Extracted graph relationship

constrained random verification USES Extracted graph relationship

Universal Verification Methodology IMPLEMENTS Extracted graph relationship

CITATIONS

1 sources

1 citations — click to collapse

[1] Complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard. Universal Verification Methodology Coverage for Bluespec RISC-V Cores