Coverage-Driven Simulation

Definition

Coverage-driven simulation is a verification methodology in which the stimulus applied to a design under test (DUT) and the checks performed against it are guided by coverage metrics. Rather than relying solely on hand-written directed tests, random or constrained-random stimulus is generated, executed against the DUT, and the resulting behavior is measured against a coverage model that encodes the design's intended features, corner cases, and architectural states.

The loop typically proceeds as:

1. Define a coverage model that expresses the design features and behaviors that must be exercised.
2. Generate constrained-random stimulus that targets under-covered bins.
3. Run the simulation against the DUT.
4. Collect coverage results, identify gaps, and refine either the stimulus constraints or the coverage model.
5. Repeat until coverage targets are met or formally closed.

Role in RISC-V Verification

Achieving complete RISC-V verification requires multiple complementary methodologies, of which coverage-driven simulation is one. Because the RISC-V ISA is extensible and modular, verification must cover the legal instruction encodings, privilege levels, exception paths, and implementation-specific microarchitectural features. Coverage-driven simulation provides a scalable mechanism for measuring progress toward that goal by combining:

• Constrained-random test generation to explore the legal stimulus space efficiently.
• Functional coverage expressed in a standard methodology to assert that architecturally interesting events have been observed.

Implementation with UVM and Google RISC-V-DV

In practice, coverage-driven simulation for RISC-V cores is commonly implemented using:

• The Universal Verification Methodology (UVM) standard, which provides the constrained-random and functional-coverage infrastructure.
• The Google RISC-V-DV open-source project, which generates UVM-compliant constrained-random instruction streams for RISC-V cores.
• Commercial or open verification IP, such as Synopsys verification solutions, which integrate with the UVM environment to record coverage and drive regressions.

This combination allows functional coverage of a RISC-V core to be expressed in standard UVM constructs while the stimulus is varied automatically to close coverage gaps, and the resulting data is aggregated across regression runs.

Related Concepts

• Constrained-random verification — the stimulus-generation technique on which coverage-driven simulation relies; coverage feedback is used to bias or extend constraints toward under-covered regions.
• Universal Verification Methodology (UVM) — the standardized methodology that implements coverage-driven simulation through its coverage, randomization, and phase machinery.
• RISC-V verification — the broader verification effort for RISC-V cores, which uses coverage-driven simulation alongside other methodologies such as formal verification and directed testing.