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ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism

Paper

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism is a paper attributed on its arXiv page to Jialin Sun and eight other authors. The available arXiv record for version 2 marks the paper as withdrawn and states that no license is available for that version due to the withdrawal.

First seen 5/30/2026
Last seen 6/5/2026
Evidence 1 chunks
Wiki v1

WIKI

Overview

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism is a paper listed on arXiv. The arXiv access page identifies the work as a PDF titled ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism and attributes it to Jialin Sun and eight other authors.

The title indicates that the work concerns CPU verification and frames ISAAC in connection with LLM-aided FPGA parallelism. The available evidence does not include the paper abstract, methodology, results, or technical details beyond the title and arXiv access metadata.

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections
ISAAC introduces → 100% 4e
The paper introduces the ISAAC tool for CPU verification.
LLM-aided FPGA Parallelism uses → 95% 3e
The paper employs LLM-aided FPGA Parallelism as its core technique.
CPU Verification evaluates → 95% 2e
The paper targets and evaluates CPU verification as its main application domain.
Jialin Sun authored by → 100% 2e
The paper is authored by Jialin Sun and 8 other authors.
CPU mentions → 95% 1e
The paper focuses on verification of CPUs, directly mentioning CPUs as the target hardware.
LLM-aided Stimulus Generation uses → 85% 1e
The paper title indicates the use of LLM-aided approaches as part of its CPU verification methodology.
FPGA Parallelism uses → 95% 1e
The paper title explicitly references FPGA Parallelism as a core technique used in the work.

LINKED ENTITIES

3 links
Jialin Sun AUTHORED_BY Extracted graph relationship
ISAAC INTRODUCES Extracted graph relationship
LLM-aided FPGA Parallelism USES Extracted graph relationship

CITATIONS

4 sources
4 citations — click to collapse
[1] The paper is titled 'ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism.' ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[2] The arXiv page attributes the paper to Jialin Sun and eight other authors. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[3] The available arXiv record for version 2 marks the paper as withdrawn. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[4] The arXiv page states that there is no license for this version because it was withdrawn. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism