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ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism

Paper WIKI v1 · 5/30/2026

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism is a paper attributed on its arXiv page to Jialin Sun and eight other authors. The available arXiv record for version 2 marks the paper as withdrawn and states that no license is available for that version due to the withdrawal.

Overview

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism is a paper listed on arXiv. The arXiv access page identifies the work as a PDF titled ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism and attributes it to Jialin Sun and eight other authors.

The title indicates that the work concerns CPU verification and frames ISAAC in connection with LLM-aided FPGA parallelism. The available evidence does not include the paper abstract, methodology, results, or technical details beyond the title and arXiv access metadata.

Availability status

The arXiv page for version 2 of the paper marks the submission as withdrawn. The same page states that there is no license for this version due to withdrawal.

CITATIONS

4 sources
4 citations
[1] The paper is titled 'ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism.' ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[2] The arXiv page attributes the paper to Jialin Sun and eight other authors. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[3] The available arXiv record for version 2 marks the paper as withdrawn. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
[4] The arXiv page states that there is no license for this version because it was withdrawn. ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism