cache

Concept

In the provided processor-verification evidence, a cache is discussed as RTL-visible processor state and control logic, including instruction-cache tag/data arrays, cache entries, valid bits, L1 ways/banks, and cache-subsystem request queues. Logic Fuzzer uses table mutators to perturb cache-related RTL memories, steer cache-bank/way utilization, and expose bugs such as a CVA6 cache-subsystem arbiter lock under artificial backpressure.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 4 chunks

Wiki v2

WIKI

Overview

In the provided evidence, a cache is a processor microarchitectural target for verification. The cache-related structures discussed include instruction-cache tag and data arrays, cache entries, valid bits, L1 cache ways and banks, and cache-subsystem FIFO/arbiter logic that handles memory requests from the instruction cache.

Cache structures targeted by Logic Fuzzer

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

table mutator ← uses 95% 2e

Table mutators fuzz cache tag arrays and valid bits to stress cache behavior.

Logic Fuzzer ← uses 100% 2e

Logic Fuzzer mutates cache tag arrays and valid bits to stress cache behavior.

LINKED ENTITIES

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table mutator USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Instruction-cache tag and data arrays can be replaced with table mutators, while instruction-cache logic reads and writes those tables through DPI and the fuzzer can supply a random instruction stream for a specific BTB tag. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[2] Table mutators allow RTL memories to be mutated, including random invalidation of cache entries and fuzzing values in already-invalid entries. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[3] In the CVA6 L1 cache example, more than 50 riscv-dv random tests showed way/bank utilization behavior, with the baseline way-selection logic preferring way 0 for the requested memory locations. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[4] Stressing under-utilized cache ways by regenerating binaries or constraining address generation may be time-consuming, require cache replacement-policy detail, and may not be supported by the tool. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[5] Mutating cache tag arrays and valid bits can steer cache accesses to a bank of interest with minimal RTL and table-mutator code changes. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[6] A CVA6 cache-subsystem bug was exposed by artificial backpressure at a FIFO full signal; the FIFO queues memory requests from the instruction cache, and the result was a system hang summarized as an arbiter lock with gnt 0. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...