Directed Test Generation

Technique

Directed Test Generation refers to the use of hand-written directed tests in verification. The provided evidence frames it as a traditional approach whose use has declined in complex microprocessor verification, where automated random and constrained-random generators are used to cover stimulus space more efficiently and control distributions across opcodes and instruction attributes.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Directed Test Generation, in the context of the provided evidence, is represented by the use of hand-written directed tests for verification. The evidence states that as microprocessor designs have grown considerably in complexity, the use of such hand-written directed tests has dwindled, with automated random test generators emerging in their place to cover the stimulus space more efficiently.^[1]

Role in processor verification

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RELATIONSHIPS

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Automated Random Test Generation ← compares with 90% 1e

Automated random test generators are presented as replacements for hand-written directed tests in verification.

Hierarchical Constrained-Random Test Generation compares with → 85% 1e

The hierarchical constrained-random approach replaces hand-written directed tests in microprocessor verification.

LINKED ENTITIES

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Synopsys VCS Constraint Solver used_by_related_generation_approach The evidence describes using the Synopsys VCS constraint solver in the hierarchical constrained-random approach.

CITATIONS

9 sources

9 citations — click to expand

[1] Directed tests in verification declined as microprocessor design complexity increased. Generating AMD microcode stimuli using VCS constraint solver

[2] Automated random test generators emerged to cover stimulus space more efficiently and create microcode test sequences with distributions across opcodes and instruction attributes. Generating AMD microcode stimuli using VCS constraint solver

[3] Traditional sequential randomization can result in verbose, redundant code and limited distribution control. Generating AMD microcode stimuli using VCS constraint solver

[4] A hierarchical constrained-random approach with the Synopsys VCS constraint solver was used to accelerate generation, reduce memory consumption, and bias generation toward corner cases. Generating AMD microcode stimuli using VCS constraint solver

[5] SystemVerilog constraint-language constructs can concisely describe microcode instruction attribute combinations and control field-value distributions. Generating AMD microcode stimuli using VCS constraint solver

[6] The described opcode generator has an upper layer using SystemVerilog random sequences with weighted knobs and a lower layer using a randomized opcode class. Generating AMD microcode stimuli using VCS constraint solver

[7] Tests are sets of weighted values that direct the generator to the required instruction mix, with the constraint solver applying weights to control opcode-type distribution. Generating AMD microcode stimuli using VCS constraint solver

[8] A single-class opcode generator is flexible but can be slow because it presents many random variables and a large constraint set to the solver. Generating AMD microcode stimuli using VCS constraint solver

[9] Partitioning opcode constraints into a base class and related opcode subclasses reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver