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Directed Test Generation

Technique WIKI v1 · 5/26/2026

Directed Test Generation refers to the use of hand-written directed tests in verification. The provided evidence frames it as a traditional approach whose use has declined in complex microprocessor verification, where automated random and constrained-random generators are used to cover stimulus space more efficiently and control distributions across opcodes and instruction attributes.

Overview

Directed Test Generation, in the context of the provided evidence, is represented by the use of hand-written directed tests for verification. The evidence states that as microprocessor designs have grown considerably in complexity, the use of such hand-written directed tests has dwindled, with automated random test generators emerging in their place to cover the stimulus space more efficiently.[1]

Role in processor verification

The cited verification context is microcode stimulus generation for microprocessor designs. Automated random test generators create microcode test sequences and emphasize distribution of stimuli across meaningful opcode values and other instruction attributes.[2]

The evidence contrasts this with traditional sequential randomization methods, which randomize instruction fields sequentially and can produce verbose, redundant code with limited control over distributions.[3]

Relationship to constrained-random generation

The article describes a hierarchical constrained-random approach using the Synopsys VCS constraint solver. This approach was used to accelerate generation, reduce memory consumption, and provide distribution control and biasing to hit corner cases.[4]

SystemVerilog constraint-language constructs are described as a way to concisely specify possible combinations of microcode-instruction attributes while precisely controlling value distributions for individual fields.[5]

Generator architecture described in the evidence

The described opcode generator uses two layers:

  • an upper layer implemented with a SystemVerilog random sequence construct and weighted knobs to control high-level item distribution; and
  • a lower layer consisting of an opcode class randomized with additional constraints and weights provided by the upper layer.[6]

The tests are sets of weighted values that direct the generator toward the required mix of instructions, and the constraint solver applies these weights to control distributions of opcode types.[7]

Implementation considerations

The evidence describes an initial single-class generator prototype in which constraints for all opcodes were defined. This design overcame flaws of sequential randomization methods, but a single-class approach can be slow because the solver must handle many random variables and a large constraint set.[8]

A later object-oriented design used a base class for global opcode constraints and subclasses for related opcode groups. Partitioning constraints hierarchically into smaller opcode groups reduced memory requirements and improved performance.[9]

Notes

The provided evidence does not give a standalone formal definition of Directed Test Generation beyond its reference to hand-written directed tests. Therefore, this article limits the description to the supported verification context and contrasts shown in the source.

[1]: Directed tests in verification; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [2]: Automated random microcode test generation; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [3]: Limitations of sequential randomization; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [4]: Hierarchical constrained-random approach and VCS constraint solver; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [5]: SystemVerilog constraint-language constructs; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [6]: Two-layer opcode-generator architecture; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [7]: Weighted tests direct generator distributions; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [8]: Single-class randomization trade-off; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc. [9]: Hierarchical partitioning into base class and subclasses; chunk 4de14aa6-a0c6-4115-8dcd-2be6148018dc.

LINKED ENTITIES

1 links
Synopsys VCS Constraint Solver used_by_related_generation_approach

CITATIONS

9 sources
9 citations
[1] Directed tests in verification declined as microprocessor design complexity increased. Generating AMD microcode stimuli using VCS constraint solver
[2] Automated random test generators emerged to cover stimulus space more efficiently and create microcode test sequences with distributions across opcodes and instruction attributes. Generating AMD microcode stimuli using VCS constraint solver
[3] Traditional sequential randomization can result in verbose, redundant code and limited distribution control. Generating AMD microcode stimuli using VCS constraint solver
[4] A hierarchical constrained-random approach with the Synopsys VCS constraint solver was used to accelerate generation, reduce memory consumption, and bias generation toward corner cases. Generating AMD microcode stimuli using VCS constraint solver
[5] SystemVerilog constraint-language constructs can concisely describe microcode instruction attribute combinations and control field-value distributions. Generating AMD microcode stimuli using VCS constraint solver
[6] The described opcode generator has an upper layer using SystemVerilog random sequences with weighted knobs and a lower layer using a randomized opcode class. Generating AMD microcode stimuli using VCS constraint solver
[7] Tests are sets of weighted values that direct the generator to the required instruction mix, with the constraint solver applying weights to control opcode-type distribution. Generating AMD microcode stimuli using VCS constraint solver
[8] A single-class opcode generator is flexible but can be slow because it presents many random variables and a large constraint set to the solver. Generating AMD microcode stimuli using VCS constraint solver
[9] Partitioning opcode constraints into a base class and related opcode subclasses reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver