Understanding UVM Coverage for RISC-V Processor Designs
PaperFirst seen 6/11/2026
Last seen 6/11/2026
Evidence 6 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
12 connectionsThe paper explains and evaluates UVM functional coverage for RISC-V processor designs.
The paper uses the Bluespec MCU RTL core as its example processor design.
Amit Goldie is listed as an author of the white paper.
Bipul Talukdar is listed as an author of the white paper.
The white paper is published by Synopsys as a white paper document.
The paper uses RISCV-DV as a core tool for the described verification methodology.
Synopsys VCS is used as the simulator in the verification methodology described in the paper.
Synopsys Verdi is used in the paper's methodology to view waveforms and coverage results.
Spike ISS is used as the golden reference for checking RTL simulation results.
Prabha Krishnaswami is listed as an author of the white paper.
The paper mentions PSS as an alternative verification technique not covered in this paper.
Rohit Narkar is listed as an author of the white paper.