DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification
PaperFirst seen 6/12/2026
Last seen 9/15/2026
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32 connectionsThe paper introduces DeepVerifier as a novel coverage-guided test generation framework.
Yuntao Lu is listed as a co-author of the paper.
Chen Bai is listed as a co-author of the paper.
Yuxuan Zhao is listed as a co-author of the paper.
Ziyue Zheng is listed as a co-author of the paper.
Yangdi Lyu is listed as a co-author of the paper.
Mingyu Liu is listed as a co-author of the paper.
Bei Yu is listed as a co-author of the paper.
The paper mentions BERT as a prominent pre-trained language model in NLP.
The paper mentions GPT as a prominent pre-trained language model in NLP.
The paper mentions RoBERTa as a prominent pre-trained language model in NLP.
The paper mentions PalmTree as a prior assembly language representation model.
The paper uses RTL models of processors as the design artifact being verified.
The paper compares DeepVerifier against simulation-based verification approaches.
The paper uses FORCE-RISCV as the random instruction stream generator for producing test sequences.
The paper proposes and uses coverage-guided verification as the central framework approach.
The paper mentions Bayesian networks as a prior ML approach to test sequence generation.
The paper uses coverage metrics as quantitative indicators to guide the verification process.
The paper uses machine learning techniques to address test generation challenges in hardware verification.
The paper discusses LSTM-based sequence modeling as a prior approach that DeepVerifier improves upon.
The paper addresses functional verification of RISC-V processor designs as its primary application domain.
The paper uses RISC-V as the target architecture for its verification framework.
The paper discusses static formal analysis as an existing approach compared to the proposed DeepVerifier method.
The paper uses Synopsys VCS as an RTL simulator to capture coverage scores from test sequences.
The paper uses Verilator as an RTL simulator to capture coverage scores from test sequences.
The paper mentions BART as a prominent deep pre-trained language model in NLP.
The paper discusses concolic testing as a competing semi-formal method for test generation.
The paper discusses coverage-guided fuzzing as a related competing approach for hardware verification.
The paper discusses Bayesian network approaches as prior ML methods for coverage modeling.
The paper discusses prior ANN-based methods for test acceleration as related work.
The paper mentions concolic testing as a semi-formal verification method.
The paper mentions static formal analysis as an alternative verification approach.