OpenHW Group

Organization

OpenHW Group is described in the supplied evidence as a not-for-profit, member-driven global organization for open-source hardware and software collaboration around RISC-V cores, related IP, tools, and software. The evidence specifically connects it to the CORE-V family, Core-V-Verif verification work, the `openhwgroup/force-riscv` GitHub repository, and transfer of CVA6 development and maintenance.

First seen 5/24/2026

Last seen 7/19/2026

Evidence 26 chunks

Wiki v3

WIKI

OpenHW Group

Overview

OpenHW Group is described in the supplied evidence as a not-for-profit, global organization driven by members and individual contributors, where hardware and software designers collaborate on open-source cores, related IP, tools, and software such as the CORE-V family of cores.^[1]

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NEIGHBORHOOD

3 nodes · 3 edges

graph · openhwgroup · depth=1

RELATIONSHIPS

11 connections

CORE-V mentions → 95% 2e

OpenHW Group develops the CORE-V processor family and its verification strategy.

Core-V-Verif ← authored by 100% 1e

Core-V-Verif is developed and maintained by the OpenHW Group.

force-riscv ← published by 1e

Force-riscv is published by the OpenHW Group.

CVA6 ← published by 100% 1e

CVA6 RISC-V CPU is published by OpenHW Group on GitHub.

RISC-V Verification Interface (RVVI) uses → 90% 1e

OpenHW Group uses RVVI for standardization of communication between testbench and RISC-V Verification IP.

CORE-V-VERIF Testbench uses → 97% 1e

The OpenHW Group uses the CORE-V-VERIF testbench for verifying their RISC-V processors.

CV32E40P introduces → 100% 1e

CV32E40P is produced by the OpenHW Group.

Core-V-Verif introduces → 95% 1e

CORE-V-VERIF is attributed to OpenHW Group as its originating organization.

CORE-V Verification Strategy ← authored by 97% 1e

The CORE-V Verification Strategy document is published by OpenHW Group.

CV32E40P updates: customizing an open-source RISC-V core at industrial-grade ← authored by 100% 1e

The paper is co-authored by Pasquale Davide Schiavone and Mike Thompson from OpenHW Group.

force-riscv uses → 100% 1e

FORCE-RISCV is maintained by the OpenHW Group.

LINKED ENTITIES

1 links

Futurewei initial_contributor_to_repository GitHub metadata describes force-riscv as an instruction set generator initially contributed by Futurewei.

CITATIONS

8 sources

8 citations — click to expand

[1] OpenHW Group organizational description [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] OpenHW infrastructure and CORE-V family description [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Core-V-Verif purpose and OpenHW development [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] Core-V-Verif UVM, verification task group, CORE-V-DOCS, and CV32E40P focus [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] Core-V-Verif testbench, BSP, random instruction generation, and test-program categories [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] GitHub metadata for openhwgroup/force-riscv openhwgroup/force-riscv

[7] force-riscv repository description as an instruction set generator initially contributed by Futurewei openhwgroup/force-riscv

[8] CVA6 development and maintenance transfer to OpenHW Group and CVA6 technical characteristics [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...