OpenHW Group

Overview

OpenHW Group is described in the supplied evidence as a not-for-profit, global organization driven by members and individual contributors, where hardware and software designers collaborate on open-source cores, related IP, tools, and software such as the CORE-V family of cores.^[1]

The evidence specifically associates OpenHW Group with:

• the CORE-V family of RISC-V open-source cores and associated subsystem IP, tools, and software;^[1]
• Core-V-Verif, a functional verification project for CORE-V RISC-V cores;^[1]
• the public GitHub repository openhwgroup/force-riscv;^[2][3]
• the transfer of CVA6 development and maintenance to OpenHW Group.^[4]

CORE-V family and infrastructure

A supplied POLITesi thesis describes OpenHW as providing infrastructure for hosting high-quality open-source hardware developments aligned with industry best practices.^[1]

The same source describes CORE-V as a series of RISC-V-based open-source cores with associated processor subsystem IP, tools, and software for electronic system designers. It states that the CORE-V family provides core IP in both silicon-optimized and FPGA-optimized implementations.^[1]

Core-V-Verif

Core-V-Verif is described as a functional verification project developed by OpenHW Group to verify the RISC-V cores of the CORE-V family.^[1]

The supplied evidence describes several technical characteristics of this verification work:

• the OpenHW Group established a Verification task group that set up a verification strategy plan;^[1]
• documentation intended to help adopters modify or extend cores is stated to be available in OpenHW Group's GitHub repository CORE-V-DOCS;^[1]
• Core-V-Verif test plans use UVM and SystemVerilog class libraries, and the verification environment is described as not specific to a single EDA vendor;^[1]
• the initial focus was verification of CV32E40P, described in the evidence as a 32-bit, power-efficient, in-order, 4-stage-pipeline RISC-V core;^[1]
• the Core-V-Verif simulation environment for CV32E40P is described as implementing the RV32IMCZifencei ISA extensions;^[1]
• the environment was expected to be adapted to other CORE-V cores, including CV32E40X, CV32E40S, CVA6, and future cores on the OpenHW roadmap plan.^[1]

Testbench and test-program support

The supplied evidence further describes the Core-V-Verif UVM environment as supporting test programs as long as they are compatible with the applicable board support package. The testbench memory module implements virtual peripherals by responding to reads or writes at specific addresses on the data bus, and board support package files align test-program resources with DUT-supported resources.^[5]

The same source states that Core-V-Verif incorporates a random instruction stream generator and supports several categories of test programs: pre-existing self-checking programs, pre-existing non-self-checking programs, generated self-checking programs, generated non-self-checking programs, and UVM tests without a test program.^[5]

GitHub namespace and force-riscv

The GitHub repository openhwgroup/force-riscv is identified by GitHub metadata as a public, non-fork repository under the openhwgroup namespace. GitHub metadata gives its canonical page URL as:

https://github.com/openhwgroup/force-riscv

and its go-import Git URL as:

https://github.com/openhwgroup/force-riscv.git

^[2]

The repository is described in GitHub page metadata as an "Instruction Set Generator initially contributed by Futurewei." The description appears in the repository page metadata, Twitter metadata, and Open Graph metadata.^[3]

CVA6 development and maintenance

A MICRO 2021 paper excerpt describes CVA6 as a RISC-V core previously known as Ariane and developed at ETH Zurich. The excerpt states that CVA6 development and maintenance had been transferred to OpenHW Group.^[4]

The same excerpt describes CVA6 as:

• written in SystemVerilog;
• a 6-stage, single-issue, in-order core;
• implementing the 64-bit RISC-V instruction set;
• capable of booting Linux;
• taped out in 22 nm technology.^[4]

Evidence-limited notes

The supplied evidence supports the relationships and technical details above. It does not provide enough information to describe OpenHW Group's full governance model, membership roster, founding history, complete project portfolio, release policies, or current maintenance status beyond the cited statements.