AI based SystemVerilog TB generation
PaperFirst seen 7/14/2026
Last seen 7/14/2026
Evidence 10 chunks
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37 connectionsThe paper cites and discusses the Markov model paper by Wagner et al.
Coverage directed test generation for functional verification using Bayesian networks mentions → 100% 2e
The paper cites Fine and Ziv's Bayesian network CDG paper.
The paper proposes a UVM-compliant testbench generation framework.
The paper extensively discusses coverage-directed generation as the central verification strategy.
The paper proposes static analysis of RTL code to extract design primitives.
The framework uses NLP to parse functional specifications.
The proposed framework employs a GNN to process the RTL graph representation.
The paper proposes combining formal verification with simulation-based approaches.
The paper discusses genetic algorithms as a prior approach to coverage-directed verification.
The paper discusses feedback-adjusted Markov models used in the StressTest tool.
The paper discusses RNNs for dynamic PRG constraint optimization.
The paper discusses the StressTest tool as an example of Markov-model-based verification.
The paper uses RTL code as the primary input to the proposed framework.
The paper compares AI-driven approaches with PRG constraint optimization.
The paper cites and discusses the RNN-based verification paper by Fajcik et al.
The paper cites and discusses Simkova and Kotasek's work on coverage-driven verification.
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage mentions → 100% 2e
The paper cites Tasiran et al.'s biased-random simulation paper.
The paper cites Goloubeva et al.'s work on automatic validation stimuli generation.
The paper cites Habibi and Tahar's work on SystemC transaction-level models.
The paper focuses on automated generation of SystemVerilog testbenches.
The author Bhavin Shah is affiliated with Techvulcan Inc.
The paper focuses on automating functional verification using AI techniques.
The paper targets ASIC design verification as its primary application domain.
The paper was published in the Journal of Scientific and Engineering Research and references IEEE publications, but the paper itself appears in JSAER.
The paper describes Bayesian networks for coverage-directed test generation.
The paper mentions Zeng et al.'s use of Constraint Logic Programming for test generation.
The paper references biased-random simulation as a prior technique for functional validation.
The paper discusses state space explosion as a key challenge for AI-based verification.
The paper discusses reward shaping as a challenge for the RL agent in the proposed framework.
The framework logs coverage data into a Unified Coverage Database (UCDB).
The paper proposes hierarchical learning as a future direction to handle large designs.
The paper recommends Explainable AI to make the ML core interpretable to verification engineers.
The paper discusses transfer learning as a mechanism to reuse knowledge across design units.
The paper mentions Abstract State Machines in the context of Habibi and Tahar's work.
The 8051 soft core processor is mentioned as the target of Goloubeva et al.'s GA-based validation.
The paper mentions the cell-based genetic algorithm proposed by Samarah et al.
The paper AI based SystemVerilog TB generation was authored by Bhavin Shah.