ASIC Design

Concept

Application-Specific Integrated Circuit (ASIC) design is the process of creating integrated circuits customized for a particular use case rather than for general-purpose use. Modern ASIC design workflows involve RTL generation, functional verification (often using SystemVerilog and UVM), logic synthesis, physical implementation (e.g., OpenLane hardening), and chip integration. As design complexity has grown, verification has become the most resource-intensive phase, and recent research has explored AI- and LLM-based approaches to automate HDL code generation, testbench creation, and end-to-end design flows.

First seen 7/14/2026

Last seen 7/14/2026

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ASIC Design

Definition and Scope

Application-Specific Integrated Circuit (ASIC) design refers to the end-to-end process of specifying, implementing, verifying, and fabricating integrated circuits tailored to a particular application, as opposed to general-purpose processors. The workflow typically spans Register Transfer Level (RTL) generation, functional verification, logic synthesis, physical design/hardening, and chip integration. Recent characterizations of the field note that "the escalating complexity of modern digital systems has imposed significant challenges on integrated circuit (IC) design, necessitating tools that can simplify the IC design flow" [arxiv:2405.02329].

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AI based SystemVerilog TB generation ← uses 100% 1e

The paper targets ASIC design verification as its primary application domain.

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CITATIONS

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[1] The escalating complexity of modern digital systems has imposed significant challenges on integrated circuit (IC) design, necessitating tools that can simplify the IC design flow. Digital ASIC Design with Ongoing LLMs: Strategies and Prospects

[2] LLMs often generate HDL code with small but critical syntax errors and struggle to accurately convey the high-level semantics of circuit designs. Digital ASIC Design with Ongoing LLMs: Strategies and Prospects

[3] An LLM-assisted three-phase PWM generator, produced as part of the Efabless AI-Generated Open-Source Chip Design Challenge, successfully passed the Design Rule Check (DRC) and was fabricated. Digital ASIC Design with Ongoing LLMs: Strategies and Prospects

[4] Large Language Models have demonstrated remarkable capabilities in Register Transfer Level (RTL) design, enabling high-quality code generation from natural language descriptions. ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation

[5] ASIC-Agent is an autonomous multi-agent system designed specifically for digital ASIC design tasks, with sub-agents for RTL generation, verification, OpenLane hardening, and Caravel chip integration. ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation

[6] ASIC-Agent-Bench is the first benchmark specifically designed to assess agentic systems in hardware design tasks. ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation

[7] As the complexity of ASIC designs continues to escalate, functional verification has emerged as the most resource-intensive phase, consuming a substantial portion of the overall development effort. AI based SystemVerilog TB generation

[8] Coverage-Driven Verification (CDV) generates stimuli with pseudo-random generators and uses coverage feedback to determine verification completeness; without proper feedback, redundant stimuli can stall coverage progress. AI based SystemVerilog TB generation

[9] AI-based SystemVerilog testbench generation aims to integrate static code analysis and machine learning to automate stimulus generation, UVM-compliant testbench code, and coverage closure within a closed-loop feedback system. AI based SystemVerilog TB generation