Abstract State Machine (ASM)

Concept

Abstract State Machines (ASMs) are a formal computational model used to specify and reason about the behavior of hardware and software systems at a high level of abstraction. ASMs have been applied in functional verification, including SystemC transaction-level modeling, where they support property checking and semantic consistency with simulation back-ends via languages such as AsmL.

First seen 7/14/2026

Last seen 7/14/2026

Evidence 1 chunks

Wiki v1

WIKI

Abstract State Machine (ASM)

Overview

Abstract State Machines (ASMs) are a formalism for describing computational systems in a rigorous, abstract way. They generalize finite state machines by allowing states with arbitrary algebraic structures (background universes) and rules that update locations in parallel, making them well suited to specifying both hardware and software behavior at varying levels of abstraction.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

AI based SystemVerilog TB generation ← mentions 95% 1e

The paper mentions Abstract State Machines in the context of Habibi and Tahar's work.

Design and Verification of SystemC Transaction-Level Models ← uses 100% 1e

The paper transforms UML system designs into Abstract State Machines for formal checking.

LINKED ENTITIES

2 links

AI based SystemVerilog TB generation MENTIONS Extracted graph relationship

Design and Verification of SystemC Transaction-Level Models USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] UML-designed systems can be transformed into ASMs using AsmL, and PSL properties can be formally checked against the resulting ASM. AI based SystemVerilog TB generation

[2] Habibi and Tahar's verification framework ensures semantic consistency via bidirectional transformation between SystemC and AsmL, and incorporates verified properties as assertion monitors. AI based SystemVerilog TB generation

[3] A logic for non-deterministic parallel ASMs handles both bounded and unbounded non-determinism while preserving completeness for single-step statements such as rule invariants, consistency conditions, and step-by-step equivalence. A Logic for Non-Deterministic Parallel Abstract State Machines

[4] An annotated bibliography of ASM-related papers was compiled as of January 1998, covering the period 1988-1998. Abstract State Machines 1988-1998: Commented ASM Bibliography