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STIMSMITH

Design and Verification of SystemC Transaction-Level Models

Paper
First seen 7/14/2026
Last seen 7/14/2026
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Tahar, Sofiène authored by → 100% 2e
Tahar, Sofiène is listed as the co-author of this paper.
Habibi, Ali authored by → 100% 2e
Habibi, Ali is listed as the first author of this paper.
AI based SystemVerilog TB generation ← mentions 100% 2e
The paper cites Habibi and Tahar's work on SystemC transaction-level models.
Assertion Coverage uses → 100% 1e
The paper targets assertion coverage as its primary metric for verification.
Genetic Algorithm (GA) uses → 100% 1e
Habibi and Tahar used a GA to enhance assertion coverage in SystemC simulation.
IEEE published by → 100% 1e
The paper was published in an IEEE Transactions journal.
Abstract State Machine (ASM) uses → 100% 1e
The paper transforms UML system designs into Abstract State Machines for formal checking.