Assertion Coverage

Concept

Assertion Coverage is a functional verification metric that quantifies how thoroughly the assertions embedded in a design (or in its verification environment) are exercised by the generated stimuli. It is widely used as a target metric in Assertion-Based Verification (ABV) and Coverage-Driven Verification (CDV), and modern research has explored AI-driven stimulus generation—particularly genetic algorithms, Markov models, and recurrent neural networks—to accelerate reaching high assertion coverage with fewer tests.

First seen 7/14/2026

Last seen 7/14/2026

Evidence 2 chunks

Wiki v1

WIKI

Definition

Assertion Coverage is a verification coverage metric that measures the fraction of design or specification assertions that have been triggered (and observed as passing or failing) during simulation, formal analysis, or hybrid verification. Whereas code coverage reports on which lines, branches, or states of the implementation were visited, assertion coverage reports on which intended behaviors, specified as assertions (e.g., SystemVerilog immediate/concurrent assertions, PSL properties, or SVA monitors), were actually exercised by the test stimulus. A design can be 100% code-covered yet still hide bugs that no assertion has ever been written to catch, which is why assertion coverage is treated as a complementary—and often more meaningful—quality gate.

Role in Assertion-Based Verification (ABV)

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Design and Verification of SystemC Transaction-Level Models ← uses 100% 1e

The paper targets assertion coverage as its primary metric for verification.

Automation and Optimization of Coverage-driven Verification ← uses 90% 1e

The paper uses GA to enhance assertion coverage.

LINKED ENTITIES

2 links

Design and Verification of SystemC Transaction-Level Models USES Extracted graph relationship

Automation and Optimization of Coverage-driven Verification USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Assertion coverage is a verification metric used in Coverage-Driven Verification (CDV) loops where stimulus generation is adapted based on coverage feedback. AI based SystemVerilog TB generation

[2] Genetic algorithms can be used to enhance assertion coverage during SystemC simulation by altering input vectors based on assertion monitor feedback rather than using purely random stimuli. AI based SystemVerilog TB generation

[3] Habibi and Tahar's SystemC transaction-level modeling approach combines UML-to-AsmL formal modeling with PSL property checking and a genetic algorithm that actively increases assertion coverage during SystemC simulation, with verified PSL properties re-instantiated as assertion monitors. AI based SystemVerilog TB generation

[4] Bayesian networks have been used by Fine and Ziv to frame coverage-directed test generation as statistical inference over probabilistic dependencies between test-generator parameters and assertion hits. AI based SystemVerilog TB generation

[5] Recurrent neural networks (RNNs), including Hopfield networks, have been integrated into closed-loop verification flows to dynamically adjust pseudo-random generator constraints from coverage/assertion feedback, optimizing for fast coverage closure. AI based SystemVerilog TB generation

[6] A genetic-algorithm-based method for automation and optimization of coverage-driven verification has demonstrated faster convergence to maximum coverage with fewer stimuli and no manual effort from the user. AI based SystemVerilog TB generation

[7] In Assertion-Based Verification (ABV) the verification plan includes code coverage, functional coverage, and assertion coverage goals, and an ABV flow on a March-algorithm MBIST controller reached 100% assertion coverage while using roughly 32% fewer tests than the maximum possible random set and achieving ~97% functional coverage. Assertion Based Functional Verification of March Algorithm Based MBIST Controller

[8] Tools such as StressTest use a Markov-model random instruction generator coupled to activity/assertion monitors; closed-loop feedback reshapes the Markov chain to concentrate stimulus on selected assertions of interest. AI based SystemVerilog TB generation

[9] Code coverage alone can be misleading because a code segment may be covered without its effect being observable at a circuit output, motivating higher-level metrics such as assertion coverage and observability-oriented tag coverage. AI based SystemVerilog TB generation