StressTest

Tool

StressTest is a microprocessor verification tool based on feedback-adjusted Markov models. It optimizes stimulus constraints during simulation by observing engineer-specified probe nodes in the design under verification and using closed-loop feedback to steer generation toward stimuli that increase switching activity and improve coverage compared with random generation.

First seen 5/28/2026

Last seen 7/14/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

StressTest is a verification tool proposed for microprocessor verification. It is described as being based on feedback-adjusted Markov Models and is used to optimize stimulus generation during simulation.

Method

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RELATIONSHIPS

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AI based SystemVerilog TB generation ← mentions 100% 2e

The paper discusses the StressTest tool as an example of Markov-model-based verification.

Microprocessor Verification via Feedback-Adjusted Markov Models ← uses 100% 2e

The StressTest tool is the implementation described in the paper by Wagner et al.

Feedback-Adjusted Markov Model uses → 100% 2e

StressTest is driven by a feedback-adjusted Markov model for random instruction generation.

Markov Model Stimulus Generation implements → 95% 1e

StressTest is a tool based on feedback-adjusted Markov Models for microprocessor verification.

LINKED ENTITIES

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Markov Model Stimulus Generation IMPLEMENTS Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] StressTest is a tool based on feedback-adjusted Markov Models proposed for microprocessor verification. [PDF] UVM-based verification of RISC-V superscalar processors

[2] StressTest performs on-the-fly optimization of stimulus constraints and requires engineer assistance to provide a template identifying points of interest or probe nodes in the design under verification. [PDF] UVM-based verification of RISC-V superscalar processors

[3] During simulation, StressTest observes probe-node activity and uses closed-loop feedback to steer the generator toward stimuli that create higher switching activity at the probing points. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The cited results reported better coverage in fewer cycles than random generation techniques. [PDF] UVM-based verification of RISC-V superscalar processors