Markov Model Stimulus Generation

Concept

Markov Model Stimulus Generation is a feedback-driven verification approach in which Markov-model-based stimulus constraints are adjusted during simulation to improve coverage or switching activity. The evidence specifically describes StressTest, a tool based on feedback-adjusted Markov Models for microprocessor verification.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Markov Model Stimulus Generation refers to the use of Markov-model-based techniques to guide stimulus generation during hardware verification. In the cited evidence, this approach appears as feedback-adjusted Markov Models used by the tool StressTest to verify microprocessors.

The broader verification problem addressed by this class of techniques is automated test application: given available directed or parameterized constrained-random sequences and functional coverage goals, the goal is to apply stimuli in a way that improves verification coverage across multiple trials.

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StressTest ← implements 95% 1e

StressTest is a tool based on feedback-adjusted Markov Models for microprocessor verification.

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StressTest IMPLEMENTS Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] StressTest is a tool based on feedback-adjusted Markov Models proposed to verify microprocessors. [PDF] UVM-based verification of RISC-V superscalar processors

[2] StressTest can optimize stimulus constraints on the fly but requires engineer assistance to provide a template describing points of interest, or probe nodes, inside the design under verification. [PDF] UVM-based verification of RISC-V superscalar processors

[3] During simulation, StressTest observes probing-node activity and uses closed-loop feedback to direct the test generator toward stimuli that create higher switching activity at the probe points. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The reported results showed better coverage in fewer cycles than random generation techniques. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The broader verification context is automated test application for maximizing verification coverage over multiple trials given constrained-random sequences and functional coverage goals. [PDF] UVM-based verification of RISC-V superscalar processors