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StressTest

Tool WIKI v1 · 5/28/2026

StressTest is a microprocessor verification tool based on feedback-adjusted Markov models. It optimizes stimulus constraints during simulation by observing engineer-specified probe nodes in the design under verification and using closed-loop feedback to steer generation toward stimuli that increase switching activity and improve coverage compared with random generation.

Overview

StressTest is a verification tool proposed for microprocessor verification. It is described as being based on feedback-adjusted Markov Models and is used to optimize stimulus generation during simulation.

Method

StressTest performs on-the-fly optimization of stimulus constraints. The workflow requires an engineer to provide a template describing points of interest inside the design under verification, also referred to as probe nodes.

During simulation, StressTest observes activity at the probe nodes. It then applies closed-loop feedback to direct the test-generator engine toward stimuli that produce higher switching activity at those probing points.

Reported effect

The cited source reports that StressTest achieved better coverage in fewer cycles than random generation techniques.

Relationship to Markov-model stimulus generation

StressTest implements a Markov-model-based approach to stimulus generation: its generation process is described as using feedback-adjusted Markov Models to steer test stimuli based on observed design activity.

CITATIONS

4 sources
4 citations
[1] StressTest is a tool based on feedback-adjusted Markov Models proposed for microprocessor verification. [PDF] UVM-based verification of RISC-V superscalar processors
[2] StressTest performs on-the-fly optimization of stimulus constraints and requires engineer assistance to provide a template identifying points of interest or probe nodes in the design under verification. [PDF] UVM-based verification of RISC-V superscalar processors
[3] During simulation, StressTest observes probe-node activity and uses closed-loop feedback to steer the generator toward stimuli that create higher switching activity at the probing points. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The cited results reported better coverage in fewer cycles than random generation techniques. [PDF] UVM-based verification of RISC-V superscalar processors