Cadence

Organization

Cadence is identified in the evidence as an organization associated with electronic-design verification: its JasperGold tool is cited in RISC-V formal-verification workflows, and Mentor and Cadence's OVM is described as one of the technology bases that fed into the Accellera UVM standard.

First seen 5/27/2026

Last seen 6/2/2026

Evidence 2 chunks

Wiki v2

WIKI

Overview

Cadence appears in the provided technical evidence in the context of electronic-design verification. Two specific associations are supported: Cadence's JasperGold is cited as a formal-verification tool used with RVFI tracing in RISC-V verification workflows, and Mentor and Cadence's OVM is described as one of the methodology streams that contributed to the Accellera Universal Verification Methodology (UVM) standard.[1][2]

Role in verification methodology

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NEIGHBORHOOD

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RELATIONSHIPS

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JasperGold uses → 90% 1e

JasperGold is a formal verification tool by Cadence used for RISC-V verification.

CITATIONS

3 sources

3 citations — click to collapse

[1] Cadence's JasperGold is cited as a formal-verification tool used with RVFI tracing in RISC-V workflows to prove equivalence between traces from a simple HDL model and a pipelined HDL implementation; the same source states limitations for in-order pipelines, specialist knowledge, and full-processor functional testing. Randomized Testing of RISC-V CPUs using Direct

[2] The Accellera UVM standard was established through collaboration between EDA vendors and clients and incorporated elements including Mentor and Cadence's OVM, alongside Mentor's AVM, Verisity's eRM, and Synopsys's VMM-RAL. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] OVM forms the core of UVM, and UVM provides a SystemVerilog class framework for verification testbenches with components such as drivers, monitors, stimulus generators, and scoreboards, with sequence items flowing through standardized components. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi