Overview

Cadence appears in the provided technical evidence in the context of electronic-design verification. Two specific associations are supported: Cadence's JasperGold is cited as a formal-verification tool used with RVFI tracing in RISC-V verification workflows, and Mentor and Cadence's OVM is described as one of the methodology streams that contributed to the Accellera Universal Verification Methodology (UVM) standard.[1][2]

Role in verification methodology

The evidence describes the Accellera UVM standard as having been established through collaboration between EDA vendors and clients. UVM drew on the existing OVM codebase and additional input from VMM; the fusion of technologies is described as including Mentor's AVM, Mentor and Cadence's OVM, Verisity's eRM, and Synopsys's VMM-RAL.[2]

In that account, OVM forms the core of UVM. UVM is described as a standardized SystemVerilog-based methodology for verifying digital designs, providing a class framework for testbenches with components such as drivers, monitors, stimulus generators, and scoreboards. Sequence items flow through standardized testbench components, supporting uniformity across verification teams and IP-integration workflows.[3]

Through the OVM connection, Cadence is therefore part of the documented lineage of reusable, scalable, and interoperable verification methodology used for complex digital-design verification.[2][3]

JasperGold in RISC-V formal verification

A separate RISC-V testing paper identifies Cadence's JasperGold as an example of a tool used with the RVFI tracing interface for model-based formal verification. In the described workflow, tools such as JasperGold are used to prove that a series of traces from a simple HDL model is equivalent to a series of traces from a pipelined HDL implementation.[1]

The same source notes limitations of this formal-verification approach: the tools discussed can handle only in-order pipelines, require specialist knowledge, and therefore do not yet replace functional testing for entire processors.[1]

Technical context

The evidence places these Cadence-related references within broader functional-verification practice. UVM addresses verification of increasingly intricate systems, while some users integrate emulation, hardware acceleration, and FPGA prototyping into functional-verification workflows. For RISC-V CPU verification, the cited testing paper contrasts formal equivalence approaches with randomized and model-based testing methods used to find divergences between executable models, simulators, and simulated hardware designs.[1][3]