Model-Based Verification

Technique

Model-Based Verification is a verification technique that checks an implementation against high-level behavioral models or model-derived properties. Evidence here covers software, cyber-physical, automotive, and RISC-V processor contexts: models can be derived from Java bytecode, transformed from EAST-ADL/Simulink/Stateflow into UPPAAL-family models, or used as golden/reference models for trace comparison in CPU verification.

First seen 5/29/2026

Last seen 5/30/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

Model-Based Verification uses an explicit behavioral model, or a model derived from an implementation, as the basis for checking whether a system satisfies intended correctness conditions. In software analysis, the technique is described as a way to express behavioral correctness conditions—such as valid execution states, variable bounds, and timing—at a high level of abstraction and then affirm that those conditions are satisfied by the software system.

The model may be hand-authored in a domain-specific modeling language, generated from program artifacts, or embodied as a reference implementation used for comparison. The common theme is that verification is driven by a model-level description of expected behavior rather than only by ad hoc tests.

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RELATIONSHIPS

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TestRIG ← uses 100% 2e

TestRIG is a pragmatic model-based verification approach that checks equivalence between a model and an implementation.

formal verification uses → 85% 2e

Model-based verification uses formal models to check equivalence between specification and implementation.

JasperGold uses → 90% 1e

JasperGold is used for formal verification of RISC-V implementations along with RVFI.

LINKED ENTITIES

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TestRIG USES Extracted graph relationship

JasperGold USES Extracted graph relationship

formal verification USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] Model-based verification expresses behavioral correctness conditions such as execution-state validity, variable bounds, and timing at a high level of abstraction and checks that software satisfies them. A Model-Derivation Framework for Software Analysis

[2] A Java software-analysis workflow can derive models from bytecode, simplify them through transformations, and output timed automata for a model checker such as UPPAAL. A Model-Derivation Framework for Software Analysis

[3] An autonomous-vehicle workflow transforms EAST-ADL/Simulink/Stateflow models into UPPAAL models with stochastic semantics and analyzes functional and non-functional properties using Simulink Design Verifier and UPPAAL-SMC. Model-based Verification and Validation of an Autonomous Vehicle System

[4] In RISC-V verification, generated test programs can be executed on both a golden model and a processor in development, with divergences detected by comparing execution traces. Randomized Testing of RISC-V CPUs using Direct

[5] TestRIG uses a Verification Engine that can stimulate RVFI-DII-compatible RISC-V implementations, use an internal RISC-V model, or compare RVFI traces from two independent implementations. Randomized Testing of RISC-V CPUs using Direct

[6] TestRIG instruction sequences may be loaded from disk, generated randomly, or produced with interactive architecture-driven state-space exploration. Randomized Testing of RISC-V CPUs using Direct

[7] QCVEngine and QuickCheck use shrinking and smart-shrinking transformations to simplify failing RISC-V instruction sequences while preserving counterexamples. Randomized Testing of RISC-V CPUs using Direct

[8] TestRIG-style sequences can include assertions, enabling failures without tandem-verification divergence and supporting tests of implementation-defined behavior. Randomized Testing of RISC-V CPUs using Direct