Overview

Model checking appears in the provided evidence as the basis for a few formal approaches in the RISC-V domain. These approaches are discussed alongside other processor-verification techniques such as directed test suites, simulation-based instruction-sequence generation, constraint-based specifications, fuzzing, and cross-level co-simulation.

Use in processor verification

The evidence states that, for RISC-V, “a few formal approaches have been proposed which are based on model checking techniques.” This places model checking among techniques used for processor verification, specifically in the context of RISC-V verification.

Limitations noted in the evidence

The cited source cautions that formal techniques, including the model-checking-based approaches it mentions, “may be susceptible to scalability issues.”