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A Methodology for Validation of Microprocessors using Equivalence Checking

Paper
First seen 6/20/2026
Last seen 6/20/2026
Evidence 10 chunks

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RELATIONSHIPS

29 connections
Golden Reference Model uses → 100% 2e
The paper generates a golden reference model from ADL specification for equivalence checking.
Functional Abstraction Technique uses → 100% 2e
The paper uses the functional abstraction technique to generate synthesizable HDL from ADL.
DLX Architecture evaluates → 100% 2e
The paper applies the methodology to the DLX architecture as a case study.
Equivalence Checking uses → 100% 2e
The paper presents a methodology that uses equivalence checking to validate microprocessors.
Pipelined Processor Validation mentions → 100% 2e
The paper addresses pipelined processor validation as its primary focus.
Synthesizable HDL Generation uses → 100% 2e
The paper uses synthesizable HDL generation from ADL specification as a key step.
EXPRESSION ADL uses → 100% 2e
The paper uses EXPRESSION ADL to capture processor structure and behavior.
ADL-driven Validation Framework introduces → 100% 2e
The paper introduces an ADL-driven validation framework for microprocessors.
Unpipelining Verification mentions → 95% 1e
The paper mentions the unpipelining verification technique as related work.
Compositional Model Checking mentions → 95% 1e
The paper mentions compositional model checking as a related technique.
Abstract State Machine mentions → 90% 1e
The paper mentions abstract state machine as used in related verification work.
ISDL mentions → 90% 1e
The paper mentions ISDL as a related ADL tool.
MIMOLA mentions → 90% 1e
The paper mentions MIMOLA as a related ADL tool.
LISA ADL mentions → 90% 1e
The paper mentions LISA as a related ADL tool.
nML mentions → 90% 1e
The paper mentions nML as a related ADL tool.
Cadence Affirma mentions → 85% 1e
The paper mentions Cadence Affirma as a related equivalence checking tool.
Mentor FormalPro mentions → 85% 1e
The paper mentions Mentor FormalPro as a related equivalence checking tool.
Verplex Conformal mentions → 85% 1e
The paper mentions Verplex Conformal as a related equivalence checking tool.
Embedded Systems mentions → 95% 1e
The paper mentions embedded systems as the target application domain.
Systems-on-Chip mentions → 95% 1e
The paper mentions Systems-on-Chip as the design context for processor validation.
Prabhat Mishra authored by → 100% 1e
Prabhat Mishra is listed as an author of the paper.
Pipeline Structure Specification mentions → 85% 1e
The paper describes pipeline structure specification as part of the EXPRESSION ADL framework.
Nikil Dutt authored by → 100% 1e
Nikil Dutt is listed as an author of the paper.
University of California Irvine published by → 100% 1e
The paper is affiliated with the University of California, Irvine.
ACES Laboratory part of → 95% 1e
The paper comes from the ACES Laboratory.
Synopsys Formality uses → 100% 1e
The paper uses Synopsys Formality as the equivalence checker in its case study.
Register Transfer Language uses → 100% 1e
The paper generates synthesizable RTL descriptions from ADL for use as reference models.
Theorem Proving mentions → 95% 1e
The paper mentions theorem proving as a related formal verification technique.
Model Checking mentions → 95% 1e
The paper mentions model checking as a related technique for processor verification.