SystemC
ToolSystemC is a C++ class library with an event-driven simulation kernel used for modeling designs at multiple abstraction levels. In the provided evidence, it is used with TLM to implement a co-simulation testbench for processor verification between an RTL core and an ISS reference model.
First seen 5/25/2026
Last seen 9/27/2026
Evidence 25 chunks
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Overview
SystemC, in combination with TLM, is described as an industry-proven modeling standard for building designs at different levels of abstraction. It is not a new programming language; it is a C++ class library that includes an event-driven simulation kernel. [SystemC nature]
Modeling model
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11 connectionsThe syntax of CRAVE is designed to fit with SystemC, implying integration and use alongside SystemC models.
SystemC is the widely accepted ESL language for Electronic System Level Design.
The experiments were conducted in a SystemC-based verification environment.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 2e
The experiments used SystemC simulation with a time limit.
SCV is the existing CRV library for SystemC models.
Transaction Level Modeling is available within SystemC as a modeling abstraction.
The SCV library is built on top of SystemC as a C++ class library.
The paper targets CRV for SystemC.
ILAtor generates ILEMs in SystemC format
SystemC is used to create formal models for model checking verification.
The SCV library layers on top of SystemC and adds verification capabilities to it.