SystemC

Tool

SystemC is a C++ class library with an event-driven simulation kernel used for modeling designs at multiple abstraction levels. In the provided evidence, it is used with TLM to implement a co-simulation testbench for processor verification between an RTL core and an ISS reference model.

First seen 5/25/2026

Last seen 6/6/2026

Evidence 6 chunks

Wiki v1

WIKI

Overview

SystemC, in combination with TLM, is described as an industry-proven modeling standard for building designs at different levels of abstraction. It is not a new programming language; it is a C++ class library that includes an event-driven simulation kernel. [SystemC nature]

Modeling model

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NEIGHBORHOOD

1 nodes · 0 edges

graph · SystemC · depth=1

RELATIONSHIPS

2 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 2e

The experiments used SystemC simulation with a time limit.

ILAtor ← uses 93% 1e

ILAtor generates ILEMs in SystemC format

LINKED ENTITIES

1 links

Co-Simulation Testbench IMPLEMENTED_IN Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] SystemC nature

[2] SystemC execution model

[3] SystemC communication

[4] TLM generic payload

[5] SystemC co-simulation use

[6] Co-simulation orchestration

[7] RTL-to-TLM interfaces