Overview

SystemC, in combination with TLM, is described as an industry-proven modeling standard for building designs at different levels of abstraction. It is not a new programming language; it is a C++ class library that includes an event-driven simulation kernel. [SystemC nature]

Modeling model

A SystemC design is structured using modules, while behavior is modeled with processes triggered by events. Process execution is non-preemptive: the simulation kernel regains control when a process finishes execution or actively suspends itself. [SystemC execution model]

Communication and TLM

SystemC communication can be implemented with signals, which are commonly used for RTL models, or abstracted using TLM transactions, which are commonly used for high-level algorithmic models. A transaction object consists essentially of a command such as read or write, a data payload, and an address. [SystemC communication]

The evidence gives a memory-interface example using a TLM generic payload (gp): the interface obtains the address, access length, and data pointer from the transaction object, then performs a read or write depending on the TLM command. [TLM generic payload]

Use in processor co-simulation

The cited processor-verification testbench is implemented in SystemC and uses TLM. It enables co-simulation between an RTL core under test and an ISS reference model. [SystemC co-simulation use]

In that testbench, a test controller orchestrates repeated execution and comparison steps: it lets the RTL core execute one instruction, lets the ISS execute the same instruction, compares their execution states—particularly registers—and reports an error if the states mismatch. [Co-simulation orchestration]

The RTL core is driven by a clock signal and uses separate memory interfaces for instruction and data memory. These memory interfaces translate between RTL core signals and TLM transactions, providing a unified memory abstraction for the RTL core and ISS based on a common standard. [RTL-to-TLM interfaces]