Skip to content
STIMSMITH

riscv-formal

Tool WIKI v1 · 5/26/2026

riscv-formal is referenced in RISC-V verification literature as a RISC-V formal verification framework and as a notable model-checking-based formal verification approach.

Overview

riscv-formal is a tool/framework in the RISC-V verification ecosystem. A 2020 paper on cross-level processor verification for RISC-V identifies riscv-formal as a notable formal verification approach that leverages model checking, and its references list it as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.

Role in RISC-V verification

The cited RISC-V verification literature distinguishes simulation- and test-generation-based approaches from formal verification approaches. In that context, riscv-formal is grouped with model-checking-based methods for RISC-V processor verification.

The same source notes that formal methods can provide correctness guarantees, but are significantly more difficult to apply than simulation-based methods and may face complexity and scalability issues. The paper argues that, because of those issues, formal methods should be complemented by simulation-based methods.

Technical context

The target domain for riscv-formal is RISC-V processor verification. The cited source describes RISC-V as an ISA with mandatory base integer instruction sets such as RV32I, RV64I, and RV128I, plus optional extensions denoted by letters such as M for integer multiplication/division and C for compressed instructions. It also notes that the privileged architecture includes execution modes, including mandatory Machine mode, and Control and Status Registers (CSRs), which are important for environment interaction, operating-system execution, and trap handling.

Repository reference

The cited bibliography entry names riscv-formal as:

“RISC-V formal verification framework,” https://github.com/SymbioticEDA/riscv-formal

CITATIONS

5 sources
5 citations
[1] riscv-formal is identified as a notable RISC-V formal verification approach leveraging model checking.
[2] riscv-formal is referenced as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.
[3] Formal methods can provide correctness guarantees, but are more difficult to apply than simulation-based methods and may have complexity and scalability issues.
[4] The RISC-V ISA includes mandatory base integer instruction sets such as RV32I, RV64I, and RV128I, plus optional extensions such as M and C.
[5] The RISC-V privileged architecture includes execution modes, including mandatory Machine mode, and Control and Status Registers used for environment interaction, operating-system execution, and trap handling.