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ISA compliance verification

Concept

ISA compliance verification is the architecture-level part of CPU verification that checks whether a processor implementation conforms to its instruction set architecture, including instructions, modes, memory-related behavior, interrupts, privilege levels, and other software-visible interfaces.

First seen 5/28/2026
Last seen 6/7/2026
Evidence 5 chunks
Wiki v1

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Definition

ISA compliance verification is the architecture-level verification activity that checks whether a CPU implementation is compliant with its Instruction Set Architecture (ISA). In the cited verification-planning context, architecture verification is needed so that software can run seamlessly on the CPU design, and its test plan should cover the ISA-visible behavior of instructions, modes, memory management, interrupts, and other software interfaces. [ISA compliance goal; Architecture-verification scope]

An ISA defines the software-visible features of a CPU, including supported instructions, data types, registers, hardware support for main memory such as virtual memory, memory consistency and addressing modes, and privilege levels. The device that executes the ISA-defined instructions is an implementation of that ISA; the ISA defines how machine code behaves across implementations, enabling binary compatibility despite differing internal designs. [ISA definition and implementation]

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RELATIONSHIPS

4 connections
riscv-formal ← implements 99% 1e
riscv-formal is the framework used to perform ISA compliance verification of RISC-V processors
instruction check ← part of 95% 1e
Instruction checks are the majority of formal checks needed to verify a core
PC check ← part of 92% 1e
PC checks are part of the formal verification of RISC-V cores
blackbox ← part of 87% 1e
Blackboxing of register file and ALU is an option in riscv-formal verification

LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship
RISC-V compliance test suite USES Extracted graph relationship
CPU Verification PART_OF Extracted graph relationship

CITATIONS

8 sources
8 citations — click to expand
[1] ISA compliance goal [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] Architecture-verification scope [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] ISA definition and implementation [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] CPU verification plan categories [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] Verification test-plan contents [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] Verification mechanisms [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[7] RISC-V CPU verification components and evaluation [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[8] RISC-V instruction-set compliance testing [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi