RISC-V compliance test suite

Concept

The RISC-V compliance test suite is referenced in the evidence as a test set available from the RISC-V organization and integrated with the RISC-V toolchain in a UVM/SystemVerilog verification infrastructure for a RISC-V CPU core. In that context it supports instruction-set compliance testing as part of a broader verification strategy that also includes Spike, random instruction generation, directed tests, and benchmarks.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 2 chunks

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Overview

The RISC-V compliance test suite is a set of tests described in the provided evidence as being available from the RISC-V organization and integrated with open-source tools in a RISC-V verification flow.[1] In the cited UVM-based RISC-V CPU-core verification thesis, the suite appears as one component of a larger infrastructure intended to help verify the correctness and reliability of a RISC-V core.[1]

Role in RISC-V core verification

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LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

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CITATIONS

3 sources

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[1] The RISC-V compliance test suite is described as available from the RISC-V organization and integrated with RISC-V toolchain tools in a UVM-based RISC-V CPU-core verification infrastructure. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The verification infrastructure also includes a random instruction generator, directed tests, benchmarks, and Spike, a RISC-V instruction set simulator used to validate correct instruction execution. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The thesis treats instruction-set compliance testing as a distinct experimental-evaluation activity. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi