Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms
PaperFirst seen 6/6/2026
Last seen 6/6/2026
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36 connectionsThe paper discusses PULP RI5CY as an in-order core for safety-critical embedded applications.
The paper discusses Chiffre as an FPGA-based fault injection platform.
The paper surveys RISC-V testability and security mechanisms.
The paper analyzes AI-assisted test generation as a key topic.
The paper analyzes statistical fault injection frameworks.
The paper analyzes design-for-test architectures.
The paper covers hardware-software co-verification methods.
The paper examines trusted execution environments as a security mechanism.
The paper discusses post-quantum cryptography in RISC-V systems.
The paper discusses Synopsys STING as a constrained-random stimulus generation tool.
The paper discusses Breker RISC-V SoCReady SystemVIP as a comprehensive verification suite.
The paper discusses FERIVer as an FPGA-assisted RTL verification framework.
The paper discusses OpenTitan as a RISC-V secure platform demonstrating hardware root of trust.
The paper discusses Rocket Core as an open RISC-V implementation.
The paper discusses BOOM as an out-of-order RISC-V processor for studying speculation.
The paper covers privilege-level fault handling as a safety feature.
The paper discusses temporal isolation in the safety domain.
The paper discusses PMP as a RISC-V isolation mechanism.
The paper discusses CHERI-RISC-V as a capability-based memory protection approach.
The paper discusses PMCs for runtime monitoring in RISC-V.
The paper discusses the RISC-V debug specification.
The paper mentions BIST as part of hybrid DfT verification strategies.
The paper discusses TestRIG as a tool using RVFI-DII interfaces for random instruction testing.
The paper discusses Vicuna as a predictable vector coprocessor for temporal isolation.
The paper covers RISC-V scalar cryptography extensions.
The paper covers RISC-V bit manipulation extensions.
The paper covers RISC-V entropy source extension.
The paper discusses RiESCUE as an open-source directed test framework.
The paper discusses DifuzzRTL as a differential fuzzing tool for RTL implementations.
The paper discusses riscv-formal as a formal property checking framework.
The paper discusses RISQ-V as a hardware/software co-design for PQC on RISC-V.
The paper is authored by Mahreen Khan.
The paper is authored by Maria Mushtaq.
The paper is authored by Ludovic Apvrille.
The paper is affiliated with Telecom Paris, Institut Polytechnique de Paris.
The paper discusses Keystone as an open-source TEE framework for RISC-V.