Built-In Self-Test (BIST)

Concept

Built-In Self-Test (BIST) is a Design-for-Test (DfT) technique in which test generation and response-analysis circuitry is integrated on-chip, enabling in-system detection of hardware faults and defects. It is widely deployed in modern Systems-on-Chip (SoCs) for both memory and logic testing, and is the subject of active research into secure and software-driven variants for RISC-V platforms.

First seen 6/6/2026

Last seen 6/6/2026

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WIKI

Overview

Built-In Self-Test (BIST) is a Design-for-Test (DfT) methodology in which a circuit block generates its own test patterns and analyzes the responses internally, removing the need for external automated test equipment to drive every test. In RISC-V SoC practice, BIST is classified alongside scan chains as a structural DfT mechanism that supports Automatic Test Pattern Generation (ATPG) workflows [Survey of Testability and Security Mechanisms, Table I, chunk 9d367313-b568-4e20-b726-3e6bf7175662, chunk ad26c765-657b-48ce-ba61-30ecb95e7f5b]. The survey lists BIST under the "Design-for-Test Architectures" category, paired with scan-chain DfT and ATPG support (citation [16] of that work).

Role in System-on-Chip Test Integration

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NEIGHBORHOOD

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RELATIONSHIPS

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Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms ← mentions 90% 1e

The paper mentions BIST as part of hybrid DfT verification strategies.

Design-for-Test (DfT) ← depends on 85% 1e

DfT strategies integrate structural scan/BIST mechanisms.

LINKED ENTITIES

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Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms MENTIONS Extracted graph relationship

Design-for-Test (DfT) DEPENDS_ON Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] BIST is a Design-for-Test technique listed in the RISC-V testability survey under 'Design-for-Test Architectures' alongside scan-chain DfT with ATPG support. Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms

[2] Modern SoCs embed BIST modules in IP blocks to handle hardware faults and defects during operation, but BIST results can leak internal DUT state and create attack vectors. Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

[3] Result compaction hides the BIST chain structure to reduce information leakage but introduces aliasing and invalid signatures. Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

[4] Software-BIST is flexible but suffers from limited observability and fault coverage. Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

[5] A low-overhead software/hardware hybrid BIST approach uses KMAC for zero-aliasing secure signatures and the SoC processor for test scheduling, demonstrated on a RISC-V-based SoC with on-chip and remote testing capability. Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

[6] A commercial DSC controller chip demonstrated a SoC test-integration platform that included embedded memory BIST, achieving short test integration cost, short test time, and small area overhead; a memory BIST compiler and SOC testing integration system were developed. SOC Testing Methodology and Practice

[7] DfT for RISC-V SoCs is evolving toward hybrid verification strategies that integrate structural scan/BIST with simulation-based frameworks and ISA-aware coverage analysis. Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms