FERIVer
ToolFirst seen 6/6/2026
Last seen 6/6/2026
Evidence 3 chunks
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2 connections Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms ← evaluates 90% 2e
The paper discusses FERIVer as an FPGA-assisted RTL verification framework.
FERIVer implements FPGA-assisted cross-validation of RTL and software models.