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Instruction Sequence

Concept

An instruction sequence is a concept used both as a theoretical abstraction of a computer program and as a practical testing artifact. Prior work treats instruction sequences as a simple conceptualization of programs, studies how they are put into effect through execution or interpretation, and uses random instruction sequences as inputs for tandem testing of CPU models and implementations.

First seen 5/27/2026
Last seen 6/8/2026
Evidence 9 chunks
Wiki v2

WIKI

Overview

An instruction sequence is used in the literature as a simple theoretical conceptualization of a computer program. In that framing, instruction sequence testing is proposed as a possible model for developing a theory of software testing.

Theoretical framing

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections
RTL Fuzzing ← uses 96% 4e
RTL fuzzing uses instruction sequences as the basic structure of its input.
Input Instruction Distillation ← uses 95% 2e
Input instruction distillation operates on instruction sequences to shorten them while maintaining coverage.
Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← uses 90% 1e
The paper uses instruction sequences as part of the custom mutation procedure.
RISC-V Torture Test Generator ← uses 90% 1e
The RISC-V Torture test generator generates valid instruction sequences.
Custom Mutation Procedure ← uses 90% 1e
The custom mutation procedure injects instruction sequences into the bytestream.

LINKED ENTITIES

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RTL Fuzzing USES Extracted graph relationship

CITATIONS

4 sources
4 citations — click to collapse
[1] Instruction sequences are used as a simple theoretical conceptualization of computer programs, and instruction sequence testing may serve as a model for a theory of software testing. About Instruction Sequence Testing
[2] Execution of an instruction sequence is a special case of directly putting it into effect, and directly putting into effect includes both interpretation and execution. Putting Instruction Sequences into Effect
[3] TestRIG checks equivalence between a model and an implementation by generating random instruction sequences, executing the same sequences on both, and comparing execution traces. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[4] With Direct Instruction Injection, the next instruction is provided by the test harness regardless of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct Instruction Injection