Compliance Testing

Concept

Compliance testing is the process of checking that an implementation conforms to a defined standard, thereby ensuring interoperability within a broader ecosystem. It is applied across domains including hardware instruction set architectures (e.g., RISC-V), regulated software systems (finance, automotive, power), and security standards (X.509 certificates), and is supported by methodologies such as mutation-based test generation, formal model-driven test generation, and LLM-assisted auto-formalization of regulatory requirements.

First seen 6/10/2026

Last seen 6/10/2026

Evidence 6 chunks

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WIKI

Definition and Purpose

Compliance testing is the process of checking whether an implementation meets a defined standard, with the goal of ensuring compatibility with a wider ecosystem. In the hardware ISA context, compliance testing checks "whether registers are missing, modes are not there, instructions are absent, corner-case scenarios are working as specified, and is performing basic functional sanity-checks for each instruction" [1].

It is distinct from formal verification: while verification attempts to prove that an implementation is correct, compliance testing attempts to show that an implementation meets the standard and thus remains interoperable with the surrounding ecosystem of tools, software development kits (SDKs), and other implementations [1].

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Mutation-based Compliance Testing for RISC-V ← uses 100% 2e

The paper addresses RISC-V compliance testing.

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Mutation-based Compliance Testing for RISC-V USES Extracted graph relationship

RISC-V APPLIED_TO RISC-V is the principal hardware architecture for which compliance testing is described in the evidence, including the official RISC-V Compliance Test-suite and the mutation-based approach.

Symbolic Execution USES The mutation-based compliance testing approach uses a symbolic execution framework (built on angr) to generate test-cases that kill surviving mutants.

CITATIONS

14 sources

14 citations — click to expand

[1] Compliance testing checks whether registers are missing, modes are not there, instructions are absent, corner-case scenarios are working as specified, and performs basic functional sanity-checks for each instruction. Mutation-based Compliance Testing for RISC-V

[2] Unlike verification, which attempts to prove correctness, compliance testing attempts to show that an implementation meets the standard and ensures compatibility with the RISC-V ecosystem. Mutation-based Compliance Testing for RISC-V

[3] RISC-V is modular, defining 32, 64, and 128 bit integer base ISAs with optional standard extensions and custom instructions, and risks ecosystem fragmentation without compliance testing. Mutation-based Compliance Testing for RISC-V

[4] A RISC-V compliance task group was formed and an official Compliance Test-suite (CT) is being actively developed, with quality monitored via functional coverage metrics. Mutation-based Compliance Testing for RISC-V

[5] The mutation-based approach defines RISC-V-tailored mutation classes that mask register and immediate values, modify constants, replace accessed registers, immediates, and operators, and check for exception side-effects. Mutation-based Compliance Testing for RISC-V

[6] The symbolic execution framework is built on angr and kills a mutant when a difference in register values, memory access addresses, read/write memory values, or PC is observed; a custom RISC-V assembly test format is used to instantiate generated test-cases. Mutation-based Compliance Testing for RISC-V

[7] On base RV32I, the official CT killed an average of around 92% of mutants across nine mutation classes in about four hours (roughly 6 seconds per mutation). Mutation-based Compliance Testing for RISC-V

[8] The specification-based CT contains 8900 additional tests and kills around half of the remaining 192 mutants in about 23 hours, but leaves certain gaps including an immediate-based shift problem. Mutation-based Compliance Testing for RISC-V

[9] The mutation-based CT killed all remaining 101 mutants in about 2.5 hours (an average of 85 seconds per mutant), producing 101 focused test-cases cross-validated on a reference ISS. Mutation-based Compliance Testing for RISC-V

[10] A configuration error in SAIL was detected via the specification-based CT (executing RV32I compliance tests with the C extension enabled), and a GRIFT bug was found via the mutation-based CT (JAL updates RD even when an unaligned instruction trap occurs). Mutation-based Compliance Testing for RISC-V

[11] Some mutants cannot be killed in a platform-independent way because they depend on a hardcoded memory address or PC value, while simulators may define their own memory layouts; proposed future work includes CSRs, additional extensions, test-suite minimization, and stronger mutation classes. Mutation-based Compliance Testing for RISC-V

[12] Related approaches for RISC-V test generation include coverage-guided fuzzing (focused on negative testing), specification-driven constraint-solving test generation (focused on positive testing with value-driven specifications), and the Scala-based Torture Test generator. Mutation-based Compliance Testing for RISC-V

[13] In regulated domains (finance, automotive, power), compliance testing is largely manual; the RAFT framework auto-formalizes requirements and generates compliance test cases by explicating tacit regulatory knowledge from multiple LLMs and integrating it into a domain meta-model, a formal requirements representation, and testability constraints, achieving expert-level performance. Explicating Tacit Regulatory Knowledge from LLMs to Auto-Formalize Requirements for Compliance Test Case Generation

[14] In security, X.509 certificate linters perform standards-compliance testing; when unsatisfactory, an Isolation Forest-based anomaly detection technique can identify anomalies beyond standards compliance, validated on Certificate Transparency logs. Anomaly Detection in Certificate Transparency Logs