Bayesian Network Test Generation
ConceptBayesian Network Test Generation is a coverage-directed test-generation (CDG) technique for functional hardware verification in which a Bayesian network models the test-generation constraints and is fine-tuned using coverage feedback from the design under test (DUT). The canonical reference is S. Fine and A. Ziv's DAC 2003 paper; later processor-verification literature cites it as an influential CDG mechanism but repeatedly notes its design-knowledge requirements, and situates it alongside genetic-programming CDG, Coverage-guided Aging, and coverage-guided fuzzing (CGF) approaches.
First seen 5/29/2026
Last seen 8/8/2026
Evidence 11 chunks
Wiki v7
WIKI
Overview
Bayesian Network Test Generation is a coverage-directed test-generation (CDG) technique in which a Bayesian network models the test-generation constraints, and the parameters of that network are fine-tuned using coverage feedback obtained from the design under test (DUT). The canonical reference in the supplied evidence is S. Fine and A. Ziv, "Coverage directed test generation for functional verification using bayesian networks," published at DAC 2003, pp. 286–291 [1] [2] [3].
Role in Coverage Directed Test Generation (CDG)
NEIGHBORHOOD
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7 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging compares with → 85% 3e
The paper discusses Bayesian network-based test generation as a related approach.
CDG mechanisms can use Bayesian networks for test generation
The paper mentions bayesian network based coverage-guided test generation as a related approach.
The paper mentions bayesian network-based test generation as a related technique.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 1e
The paper mentions coverage directed test generation based on Bayesian networks as related work.
Bayesian network test generation is a specific model-based test generation approach.
The paper mentions coverage-directed test generation using Bayesian networks as a related technique.
LINKED ENTITIES
6 linksEfficient Cross-Level Processor Verification using Coverage-guided Fuzzing MENTIONS Extracted graph relationship
Coverage-Directed Test Generation IS_A Bayesian Network Test Generation is described in the evidence as a representative instance of the broader CDG class of mechanisms.
EPEX: Processor Verification by Equivalent Program Execution MENTIONED_BY The EPEX GLSVLSI 2021 paper explicitly mentions coverage-guided test generation based on Bayesian networks when discussing test-program generation approaches for RISC-V.
Mutation-based Compliance Testing for RISC-V MENTIONED_BY The ASP-DAC 2021 compliance-testing survey lists Bayesian-network-based CDG among notable alternative approaches.
Verifying Instruction Set Simulators using Coverage-guided Fuzzing MENTIONED_BY The DATE 2019 ISS-fuzzing paper lists Bayesian-network-based coverage-guided test generation among notable alternative approaches.
Coverage-guided Aging ALTERNATIVE_APPROACH Coverage-guided Aging is presented in the 2022 DATE paper as an alternative endless-stream coverage-guided approach, compared against coverage-guided test generation based on Bayesian networks.
CITATIONS
9 sources9 citations — click to expand
[1] The canonical reference for Bayesian-network-based coverage-directed test generation is S. Fine and A. Ziv, 'Coverage directed test generation for functional verification using bayesian networks,' DAC 2003, pp. 286–291. Fine and Ziv, DAC 2003 (via supplied evidence)
[2] Bayesian-network-based CDG is a representative instance of CDG mechanisms, sitting on a spectrum that trades off domain knowledge against general applicability, and is listed alongside genetic-programming-based generation (MicroGP) and Markov-chain-based frameworks. CDG survey discussion (supplied evidence)
[3] In the Fine and Ziv formulation, a Bayesian network encodes dependencies between test-generation parameters, and its parameters are adjusted according to coverage feedback from the DUT to drive the test generator toward uncovered RTL regions. Fine and Ziv, DAC 2003 (via supplied evidence)
[4] The EPEX paper (GLSVLSI 2021) lists coverage-guided test generation based on Bayesian networks among alternative approaches and characterizes them as 'either not designed for RTL verification, require a lot of effort until thorough tests are generated, or do not target the RISC-V ISA.' EPEX: Processor Verification by Equivalent Program Execution (GLSVLSI 2021)
[5] The 2022 DATE cross-level processor-verification paper lists Bayesian-network-based coverage-guided test generation as related work and groups it with approaches that are either not designed for RTL verification, restrict the generated instruction streams, or do not target the modern RISC-V ISA. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing (DATE 2022)
[6] The same 2022 DATE paper reports that its proposed Coverage-guided Aging generator yields a more regular coverage distribution than a static randomized generator, with weaker peaks and no visible gaps across instruction-group combinations such as 'Special & System : Special & System' and 'Other : Other.' Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing (DATE 2022)
[7] The ASP-DAC 2021 'Mutation-based Compliance Testing for RISC-V' paper lists Bayesian-network-based CDG among notable alternative approaches that, while influential for general verification, do not directly target RISC-V compliance testing. Mutation-based Compliance Testing for RISC-V (ASP-DAC 2021, supplied evidence)
[8] The DATE 2019 ISS-coverage-guided-fuzzing paper lists coverage-guided test generation based on Bayesian networks among 'other notable approaches' for improving random processor-level stimulus generation. Verifying Instruction Set Simulators using Coverage-guided Fuzzing (DATE 2019, supplied evidence)
[9] The CDG survey discussion characterizes Bayesian-network-based CDG as having a non-straightforward initial setup that requires in-depth expertise in the RTL design specifications. CDG survey discussion (supplied evidence)