Bayesian Network Test Generation

Concept

Bayesian Network Test Generation is a coverage-directed test-generation (CDG) technique for functional hardware verification in which a Bayesian network encodes dependencies between test-generation parameters and its parameters are fine-tuned using coverage feedback from the design under test (DUT). The canonical reference is S. Fine and A. Ziv's 2003 DAC paper, and it is repeatedly cited in later hardware- and processor-verification literature as an influential but design-knowledge-intensive CDG mechanism, positioned alongside Markov-chain CDG, genetic-programming-based CDG (e.g., MicroGP), Coverage-guided Aging, and coverage-guided fuzzing (CGF).

First seen 5/29/2026

Last seen 6/22/2026

Evidence 10 chunks

Wiki v6

WIKI

Overview

Bayesian Network Test Generation is a coverage-directed test-generation (CDG) technique in which a Bayesian network models the test-generation constraints, and the parameters of that network are fine-tuned using coverage feedback obtained from the design under test (DUT). The canonical reference in the supplied evidence is S. Fine and A. Ziv, "Coverage directed test generation for functional verification using bayesian networks," published at DAC 2003, pp. 286–291 ^[1] ^[2] ^[3].

Role in Coverage Directed Test Generation (CDG)

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging compares with → 85% 3e

The paper discusses Bayesian network-based test generation as a related approach.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← mentions 85% 2e

The paper mentions bayesian network based coverage-guided test generation as a related approach.

Coverage-Directed Test Generation ← uses 85% 2e

CDG mechanisms can use Bayesian networks for test generation

Model-Based Test Generation part of → 80% 1e

Bayesian network test generation is a specific model-based test generation approach.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 1e

The paper mentions coverage directed test generation based on Bayesian networks as related work.

Mutation-based Compliance Testing for RISC-V ← mentions 85% 1e

The paper mentions coverage-directed test generation using Bayesian networks as a related technique.

LINKED ENTITIES

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Coverage-Directed Test Generation see_also Bayesian Network Test Generation is repeatedly characterized as an instance of the broader Coverage Directed Test Generation class of mechanisms.

CITATIONS

8 sources

8 citations — click to expand

[1] The canonical reference for Bayesian Network Test Generation is S. Fine and A. Ziv, "Coverage directed test generation for functional verification using bayesian networks," DAC 2003, pp. 286–291. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (DATE 2022)

[2] Bayesian Network Test Generation is an instance of Coverage Directed Test Generation in which the parameters of a Bayesian network are fine-tuned using coverage feedback from the DUT. Thesis on fuzzing in software and hardware domains

[3] Setting up the Bayesian network is not straightforward and requires in-depth expertise in the design specifications of the RTL design. Thesis on fuzzing in software and hardware domains

[4] CDG mechanisms are usually either DUT-specific or require in-depth design knowledge for the initial setup. Thesis on fuzzing in software and hardware domains

[5] EPEX (GLSVLSI 2021) characterizes coverage-guided test generation based on Bayesian networks as not designed for RTL verification, requiring a lot of effort until thorough tests are generated, and not targeting the RISC-V ISA. EPEX: Processor Verification by Equivalent Program Execution (GLSVLSI 2021)

[6] The 2019 DATE paper on coverage-guided fuzzing for ISSs lists coverage-guided test generation based on Bayesian networks among other notable approaches to improving processor-level stimulus generation. Verifying Instruction Set Simulators using Coverage-guided Fuzzing (DATE 2019)

[7] The 2021 ASP-DAC paper on Mutation-based Compliance Testing lists coverage-guided test generation based on Bayesian networks as a notable non-RISC-V-specific approach to test-program generation. Mutation-based Compliance Testing for RISC-V (ASP-DAC 2021)

[8] The 2022 DATE cross-level processor verification paper treats Bayesian-network-based CDG as related work and notes its limitations for RTL verification and modern RISC-V ISA targets. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (DATE 2022)